Design-Oriented Mixed-Level Circuit and Device Simulation

David A. Gates

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M93/51
June 1993

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/ERL-93-51.pdf

Integrated circuits (ICs) are the building blocks of modern computing and communication systems. The design of high complexity ICs has been enabled by the development of a large number of computer-aided design (CAD) tools for IC design (ICCAD). Mixed-level circuit and device simulation has begun to find its place as a CAD tool for the development of new IC technologies. In this dissertation, problems associated with providing support for mixed-level circuit and device simulation in an expanded role as an ICCAD tool are investigated.

Four issues of concern for a mixed-level simulator have focused this research: reliability, utility, portability, and performance. A new mixed-level circuit and device simulator called CIDER has been developed to address these concerns. The first three concerns are addressed in a serially executing version of CIDER. To obtain reliable simulation results, new models for physical effects that are important in present-day IC technologies are included in CIDER. An enhanced user-interface has been developed to increase the utility of CIDER. Finally, CIDER has been ported to a variety of engineering workstations.

The final concern, performance, is addressed in a version of CIDER that runs on distributed-memory multicomputers. The need for parallel computing is established by measuring the serial performance of CIDER. Single workstations are roughly 10 to 100 times too slow to support design of reasonably sized circuits.

Algorithms for exploiting parallelism in mixed-level simulation are reviewed, and an architecture is proposed for a parallel circuit and device simulator. A limited form of the proposed approach has been implemented on two multicomputers: a hypercube supercomputer and a cluster of engineering workstations. On a set of benchmark circuits, a best speedup of 12 on 16 processors of the hypercube is achieved. Unfortunately, the implemented approach has a number of limitations that are identified here for the first time.

Several applications of CIDER are presented that demonstrate the new parallel capability. In each application, the circuits contain multiple numerically modeled devices. The hypercube version of CIDER is used to simulate these circuits in a reasonable amount of time. New insight into these circuits is obtained by examining simulation results.

Advisor: Ping K. Ko

BibTeX citation:

@phdthesis{Gates:M93/51,
    Author = {Gates, David A.},
    Title = {Design-Oriented Mixed-Level Circuit and Device Simulation},
    School = {EECS Department, University of California, Berkeley},
    Year = {1993},
    Month = {Jun},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2382.html},
    Number = {UCB/ERL M93/51},
    Abstract = {Integrated circuits (ICs) are the building blocks of modern computing
and communication systems. The design of high complexity ICs has
been enabled by the development of a large number of computer-aided
design (CAD) tools for IC design (ICCAD). Mixed-level circuit and
device simulation has begun to find its place as a CAD tool for the
development of new IC technologies. In this dissertation, problems
associated with providing support for mixed-level circuit and device
simulation in an expanded role as an ICCAD tool are investigated.

Four issues of concern for a mixed-level simulator have focused
this research: reliability, utility, portability, and performance. A
new mixed-level circuit and device simulator called CIDER has been
developed to address these concerns. The first three concerns are 
addressed in a serially executing version of CIDER. To obtain
reliable simulation results, new models for physical effects
that are important in present-day IC technologies are included in
CIDER. An enhanced user-interface has been developed to increase
the utility of CIDER. Finally, CIDER has been ported to a variety
of engineering workstations.

The final concern, performance, is addressed in a version of
CIDER that runs on distributed-memory multicomputers. The need for
parallel computing is established by measuring the serial performance
of CIDER.  Single workstations are roughly 10 to 100 times too slow
to support design of reasonably sized circuits.

Algorithms for exploiting parallelism in mixed-level simulation are
reviewed, and an architecture is proposed for a parallel circuit
and device simulator. A limited form of the proposed approach has
been implemented on two multicomputers: a hypercube supercomputer
and a cluster of engineering workstations. On a set of benchmark
circuits, a best speedup of 12 on 16 processors of the hypercube
is achieved. Unfortunately, the implemented approach has a number
of limitations that are identified here for the first time.

Several applications of CIDER are presented that demonstrate the
new parallel capability. In each application, the circuits contain
multiple numerically modeled devices. The hypercube version of
CIDER is used to simulate these circuits in a reasonable amount
of time. New insight into these circuits is obtained by examining
simulation results.}
}

EndNote citation:

%0 Thesis
%A Gates, David A.
%T Design-Oriented Mixed-Level Circuit and Device Simulation
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/51
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2382.html
%F Gates:M93/51