Timing Analysis and Optimization for High-Performance Digital Circuits

Yuji Kukimoto

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M99/42
September 1999

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1999/ERL-99-42.pdf

Advisor: Robert K. Brayton


BibTeX citation:

@phdthesis{Kukimoto:M99/42,
    Author = {Kukimoto, Yuji},
    Title = {Timing Analysis and Optimization for High-Performance Digital Circuits},
    School = {EECS Department, University of California, Berkeley},
    Year = {1999},
    Month = {Sep},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1999/3722.html},
    Number = {UCB/ERL M99/42}
}

EndNote citation:

%0 Thesis
%A Kukimoto, Yuji
%T Timing Analysis and Optimization for High-Performance Digital Circuits
%I EECS Department, University of California, Berkeley
%D 1999
%@ UCB/ERL M99/42
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1999/3722.html
%F Kukimoto:M99/42