Jong Ho Park

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2025-202

December 17, 2025

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-202.pdf

The AI revolution is creating an unsustainable dual power crisis for the semiconductor industry. Modern fabrication plants already consume over 10 TWh annually for manufacturing, while the operational power demand from AI chips is projected to surge to over 652 TWh by 2030. This exponential growth, exemplified by proposed 5-Gigawatt scale data centers, reveals an urgent and fundamental need for new energy-efficient transistors capable of overcoming the 60 mV/decade Boltzmann Tyranny. In this dissertation, I present the design, fabrication, and analysis of advanced logic devices integrating a ferroelectric HfO2-ZrO2 superlattice to achieve this goal. First, I establish a critical component for modern Multi-Vth design by demonstrating precise threshold voltage modulation in NCFETs through systematic work function engineering. Building on this, the core of this work details the development of a novel Gate-All-Around (GAA) NCFET process, including the successful release of Si nanowires and conformal integration of the NC gate stack. Comprehensive characterization confirms superior electrostatic control and a capacitance boost from the NC effect, achieving a record-high intrinsic transconductance (2.15mS/μm) and near-ideal switching down to Leff = 25nm. Finally, I investigate transport physics in the quantum confinement regime by fabricating extremely thin-channel (3 nm) SOI devices. Repopulation of electrons in different subbands in Si reduced effective mass and higher injection velocity and I demonstrated those enhanced performances experimentally. This work collectively validates the GAA NCFET architecture as a promising solution for energy-efficient computing, and the thesis concludes with a summary and a perspective on future research.

Advisors: Sayeef Salahuddin

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BibTeX citation:

@phdthesis{Park:EECS-2025-202,
    Author= {Park, Jong Ho},
    Title= {Design and Characterization of High Performance and Energy-efficient Devices Using Negative Capacitance High-K Gate Stack},
    School= {EECS Department, University of California, Berkeley},
    Year= {2025},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-202.html},
    Number= {UCB/EECS-2025-202},
    Abstract= {The AI revolution is creating an unsustainable dual power crisis for the semiconductor industry. Modern fabrication plants already consume over 10 TWh annually for manufacturing, while the operational power demand from AI chips is projected to surge to over 652 TWh by 2030. This exponential growth, exemplified by proposed 5-Gigawatt scale data centers, reveals an urgent and fundamental need for new energy-efficient transistors capable of overcoming the 60 mV/decade Boltzmann Tyranny.
In this dissertation, I present the design, fabrication, and analysis of advanced logic devices integrating a ferroelectric HfO2-ZrO2 superlattice to achieve this goal. First, I establish a critical component for modern Multi-Vth design by demonstrating precise threshold voltage modulation in NCFETs through systematic work function engineering. Building on this, the core of this work details the development of a novel Gate-All-Around (GAA) NCFET process, including the successful release of Si nanowires and conformal integration of the NC gate stack. Comprehensive characterization confirms superior electrostatic control and a capacitance boost from the NC effect, achieving a record-high intrinsic transconductance (2.15mS/μm) and near-ideal switching down to Leff = 25nm. Finally, I investigate transport physics in the quantum confinement regime by fabricating extremely thin-channel (3 nm) SOI devices. Repopulation of electrons in different subbands in Si reduced effective mass and higher injection velocity and I demonstrated those enhanced performances experimentally. This work collectively validates the GAA NCFET architecture as a promising solution for energy-efficient computing, and the thesis concludes with a summary and a perspective on future research.},
}

EndNote citation:

%0 Thesis
%A Park, Jong Ho 
%T Design and Characterization of High Performance and Energy-efficient Devices Using Negative Capacitance High-K Gate Stack
%I EECS Department, University of California, Berkeley
%D 2025
%8 December 17
%@ UCB/EECS-2025-202
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-202.html
%F Park:EECS-2025-202