Jerry Zhao

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2025-210

December 18, 2025

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-210.pdf

As we move deeper into the "post-Moore" era, two trends have emerged as defining forces in computer architecture. At the architectural level, modern RISC-like ISAs have become the dominant foundation of programmable compute. At the microarchitectural level, continued improvements in performance and efficiency increasingly rely on specialization, rather than general-purpose capability. This thesis argues that RISC-like architectures provide an effective basis for exploiting specialized microarchitectures.

First, I develop a representative VLIW architecture and its associated microarchitecture tailored for specialized cores. Through an empirical comparison with a similarly targeted superscalar RISC design, I show that superscalar RISC-style microarchitectures impose a negligible overhead over VLIW designs for specialized cores. I next show that complex vector extensions, often perceived as antithetical to RISC principles, actually follow the modern RISC design philosophy by providing a minimal programmer or compiler interface to a capable general-purpose vector microarchitecture. I present the microarchitecture and evaluation of a compact, full-featured, and easily programmable vector unit that exemplifies this approach. I then describe a system for extending the scope of RISC instruction-driven control beyond the core boundary. By designing a system for orchestrating system-wide resources using standard RISC instructions, I demonstrate how RISC can serve as a unifying abstraction across increasingly heterogeneous multi-accelerator systems. Finally, I present a methodology for silicon-based evaluation of specialized SoCs, culminating in the design, fabrication, and testing of multiple prototype test chips that collectively embody the ideas presented in this thesis.

Advisors: Borivoje Nikolic and Krste Asanović

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BibTeX citation:

@phdthesis{Zhao:EECS-2025-210,
    Author= {Zhao, Jerry},
    Title= {Microarchitectural Techniques for Instruction-driven Specialization},
    School= {EECS Department, University of California, Berkeley},
    Year= {2025},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-210.html},
    Number= {UCB/EECS-2025-210},
    Abstract= {As we move deeper into the "post-Moore" era, two trends have emerged as defining forces in computer architecture. At the architectural level, modern RISC-like ISAs have become the dominant foundation of programmable compute. At the microarchitectural level, continued improvements in performance and efficiency increasingly rely on specialization, rather than general-purpose capability. This thesis argues that RISC-like architectures provide an effective basis for exploiting specialized microarchitectures.

First, I develop a representative VLIW architecture and its associated microarchitecture tailored for specialized cores. Through an empirical comparison with a similarly targeted superscalar RISC design, I show that superscalar RISC-style microarchitectures impose a negligible overhead over VLIW designs for specialized cores. I next show that complex vector extensions, often perceived as antithetical to RISC principles, actually follow the modern RISC design philosophy by providing a minimal programmer or compiler interface to a capable general-purpose vector microarchitecture. I present the microarchitecture and evaluation of a compact, full-featured, and easily programmable vector unit that exemplifies this approach. I then describe a system for extending the scope of RISC instruction-driven control beyond the core boundary. By designing a system for orchestrating system-wide resources using standard RISC instructions, I demonstrate how RISC can serve as a unifying abstraction across increasingly heterogeneous multi-accelerator systems. Finally, I present a methodology for silicon-based evaluation of specialized SoCs, culminating in the design, fabrication, and testing of multiple prototype test chips that collectively embody the ideas presented in this thesis.},
}

EndNote citation:

%0 Thesis
%A Zhao, Jerry 
%T Microarchitectural Techniques for Instruction-driven Specialization
%I EECS Department, University of California, Berkeley
%D 2025
%8 December 18
%@ UCB/EECS-2025-210
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-210.html
%F Zhao:EECS-2025-210