Yukio Miyasaka

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2025-214

December 19, 2025

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-214.pdf

High-effort logic synthesis is a new paradigm in logic synthesis. It is motivated by recent design trends, including AI accelerators and edge computing devices, where more resources, compared to the traditional design flows, can be allocated for optimization of some blocks due to the high reusability and repeatability of these blocks. With more runtime available, we revisit a concept of redundancy analysis, which is a formal approach to remove redundancies in logic circuits, but has been avoided due to its computational complexity. On the other hand, redundancy analysis can also be applied to redundancy addition. Iteratively performing redundancy addition and removal can open up an enormous search space, leading to improved quality compared to other conventional methods, given sufficient exploration time. Moreover, it can derive more unique structures that potentially improve some indirect metrics, such as verification runtime, as the reasoning process is influenced by structural differences. In this work, we develop a framework that integrates an efficient, resource-aware implementation of redundancy analysis into a modular design to support a variety of practical applications. To demonstrate its capabilities, we present applications to high-effort logic optimization and approximate logic synthesis. While high-effort logic optimization shares the same goal as traditional logic optimization but allotted a longer runtime, approximate logic synthesis leverages the characteristics of AI inference hardware, where the function does not have to be maintained strictly as long as it enables more efficient hardware without a significant loss of accuracy. Additionally, we investigate structural variants derived from redundancy addition and removal, compared to those derived from traditional algorithms, through assessments of physical design quality and model checking performance.

Advisors: John Wawrzynek

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BibTeX citation:

@phdthesis{Miyasaka:EECS-2025-214,
    Author= {Miyasaka, Yukio},
    Title= {High-Effort Logic Synthesis},
    School= {EECS Department, University of California, Berkeley},
    Year= {2025},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-214.html},
    Number= {UCB/EECS-2025-214},
    Abstract= {High-effort logic synthesis is a new paradigm in logic synthesis.
It is motivated by recent design trends, including AI accelerators and edge computing devices, where more resources, compared to the traditional design flows, can be allocated for optimization of some blocks due to the high reusability and repeatability of these blocks.
With more runtime available, we revisit a concept of redundancy analysis, which is a formal approach to remove redundancies in logic circuits, but has been avoided due to its computational complexity.
On the other hand, redundancy analysis can also be applied to redundancy addition.
Iteratively performing redundancy addition and removal can open up an enormous search space, leading to improved quality compared to other conventional methods, given sufficient exploration time.
Moreover, it can derive more unique structures that potentially improve some indirect metrics, such as verification runtime, as the reasoning process is influenced by structural differences.
In this work, we develop a framework that integrates an efficient, resource-aware implementation of redundancy analysis into a modular design to support a variety of practical applications.
To demonstrate its capabilities, we present applications to high-effort logic optimization and approximate logic synthesis.
While high-effort logic optimization shares the same goal as traditional logic optimization but allotted a longer runtime, approximate logic synthesis leverages the characteristics of AI inference hardware, where the function does not have to be maintained strictly as long as it enables more efficient hardware without a significant loss of accuracy.
Additionally, we investigate structural variants derived from redundancy addition and removal, compared to those derived from traditional algorithms, through assessments of physical design quality and model checking performance.},
}

EndNote citation:

%0 Thesis
%A Miyasaka, Yukio 
%T High-Effort Logic Synthesis
%I EECS Department, University of California, Berkeley
%D 2025
%8 December 19
%@ UCB/EECS-2025-214
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-214.html
%F Miyasaka:EECS-2025-214