Chun-Yen Wu

EECS Department, University of California, Berkeley

Technical Report No. UCB/

May 1, 2026

Analog circuit sizing remains a highly iterative and time-intensive process that relies heavily on human knowledge. Reinforcement learning (RL) is a promising approach for analog circuit sizing, but its practical use is hindered by low sample efficiency and long runtime. In this work, we propose SPEEDY, a RL framework for efficient design space exploration via parallel simulations and incremental pruning of the design space. SPEEDY employs a multi-actor, single-critic architecture that enables parallel exploration of candidate designs. To further enhance sample efficiency, the problem is reformulated as a single-step RL task, and a dynamic actor training strategy is introduced to guide exploration toward high-quality regions of the design space. In addition, a customized critic network is developed to allow the framework to progressively refine the feasible design range and reduce unnecessary simulations. Evaluated on a set of amplifier topologies derived from the AnalogGym benchmarks, SPEEDY achieves the highest pass rate while improving the figure of merit with respect to comparable baseline methods. On two operational transconductance amplifier topologies and one state-of-the-art low-dropout regulator design, SPEEDY with the proposed incremental refinement method achieves more than 1.4× overall runtime improvement and the best figure of merit.

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BibTeX citation:

@mastersthesis{Wu:32128,
    Author= {Wu, Chun-Yen},
    Editor= {Yao, Chun-Yen and Muller, Rikky and Nuzzo, Pierluigi},
    Title= {Single-Step Reinforcement Learning Framework for Efficient Analog Circuit Sizing Optimization},
    School= {EECS Department, University of California, Berkeley},
    Year= {2026},
    Month= {May},
    Number= {UCB/},
    Note= {Earlier and alternate versions of this thesis work have been submitted to major EDA conferences. A version titled “SPEEDY: Single-Step Reinforcement Learning Framework for Efficient Analog Circuit Sizing Optimization” was previously submitted to DAC 2026, and a revised version is currently under review for ICCAD 2026. This thesis consolidates and expands upon the methodologies, experiments, and analyses presented in these submissions.},
    Abstract= {Analog circuit sizing remains a highly iterative and time-intensive process that relies heavily on human knowledge. Reinforcement learning (RL) is a promising approach for analog circuit sizing, but its practical use is hindered by low sample efficiency and long runtime. In this work, we propose SPEEDY, a RL framework for efficient design space exploration via parallel simulations and incremental pruning of the design space. SPEEDY employs a multi-actor, single-critic architecture that enables parallel exploration of candidate designs. To further enhance sample efficiency, the problem is reformulated as a single-step RL task, and a dynamic actor training strategy is introduced to guide exploration toward high-quality regions of the design space. In addition, a customized critic network is developed to allow the framework to progressively refine the feasible design range and reduce unnecessary simulations. Evaluated on a set of amplifier topologies derived from the AnalogGym benchmarks, SPEEDY achieves the highest pass rate while improving the figure of merit with respect to comparable baseline methods. On two operational transconductance amplifier topologies and one state-of-the-art low-dropout regulator design, SPEEDY with the proposed incremental refinement method achieves more than 1.4× overall runtime improvement and the best figure of merit.},
}

EndNote citation:

%0 Thesis
%A Wu, Chun-Yen 
%E Yao, Chun-Yen 
%E Muller, Rikky 
%E Nuzzo, Pierluigi 
%T Single-Step Reinforcement Learning Framework for Efficient Analog Circuit Sizing Optimization
%I EECS Department, University of California, Berkeley
%D 2026
%8 May 1
%@ UCB/
%F Wu:32128