MEM (Micro-Electro-Mechanical) logic devices for ultra-low-power circuits (MEMS relay)

Chuang Qian, Tsu-Jae King Liu and Vladimir Stojanovic

National Science Foundation

The energy efficiency of CMOS logic circuits is fundamentally limited by the non-zero OFF-state leakage (IOFF) and subthreshold swing (SS) of a transistor, so that there exists a lower limit for energy consumed per digital operation regardless of circuit speed. Mechanical switches can achieve zero IOFF and have abrupt switching behavior, they can overcome this energy-efficiency limit. Therefore, nano-electro-mechanical (NEM) logic relays recently have been investigated for ultra-low-power digital computing.

Figure 1
Figure 1: Chuang Qian

[1]
C.Qian, et al., “Energy-Delay Performance Optimization of NEM Logic Relay,” in IEEE Int. Electron Devices Meeting Tech. Dig. (IEDM), Washington D.C., Dec. 7-9, 2015.
[2]
“Effect of Body Biasing on the Energy-Delay Performance of Logic Relays,” in IEEE Electron Device Lett., vol. 36, no. 8, pp. 862–864, Aug. 2016.