Time: 2:00pm to 4:00pm
Location: 5th floor, Soda Hall
The heart of our research agenda at the Parallel Computing Laboratory is the development of parallel software. This agenda is driven by compelling applications developed by domain experts in the many areas of expertise: applications, software engineering, programming languages, libraries, testing, operating systems, and computer architecture. We focus on exciting new applications in the areas of personal health, image retrieval, music, speech understanding, and web browsers‐ areas that need much more computing horsepower to run well, rather than on legacy programs that already run well on today's computers. The Par Lab is the result of Berkeley being the unanimous top choice by Intel and Microsoft for a $10M, 5-year Universal Parallel Computing Research Center. Samsung Electronics is our affiliate member.
Poster Session:
- SIMD Tree Computations in Browsers using SIMTask Parallelism
- Macroscopic Tree Optimizations for Multicore Webpage Layout
- MRI Parallel Imaging Eigen-Calibration and Stabilized l1-SPIRiT
- CS195-15: Engineering Parallel Software
- Video object segmentation / Combining image contour detection & optical flow
- Preserving Interactivity of GUI Applications
- Tessellation OS
- PACORA: Performance-Aware Convex Optimization for Resource Allocation Communication Avoiding QR for GPUs
- Datacenter in a Box
- Efficient Data Race Detection for UPC
- Modeling communication-avoiding linear algebra algorithms on heterogeneous architectures
- Programming with Graphical Traces
- Efficient sparse matrix code from high-level specification
- Sketching GPU optimizations
- A Speech Recognition Application Framework
for Highly Parallel Implementations on the GPU - Design Space Exploration of a Real-time Object Recognition System
- Specifying and Checking Semantic Atomicity for Multithreaded Programs
- NDSeq: Specifying and Checking Parallelism Correctness Using Nondeterministic Sequential Programs
- Avoiding Communication in Two-sided Krylov Subspace Methods A RISC-V Vector Processor in ASIC and FPGA
- Hypergraph Partitioning for Computing Matrix Powers Parallelizing Machine Translation SEJITS Framework for Gaussian Mixture Model Training Composition of SEJITS Specializers: Progress and Challenges
- Speaker Diarization: Feeding the Need for Speed
- A communication-optimal 2.5D LU factorization algorithm
- A new algorithm for heterogeneous band LU factorization in MAGMA HW/SW Codesign for Multiprocessors
- Hardware Accelerator for Graph Algorithms
- SEJITS Specializer for the Matrix Powers Kernel