Klaus Erik Schauser and Krste Asanović and David A. Patterson and Edward H. Frank

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-91-641

, 1991

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1991/CSD-91-641.pdf

In this report we compare the cost and performance of a new kind of restricted instruction cache architecture -- the stall cache -- against several other conventional cache architectures. The stall cache minimizes the size of an on-chip instruction cache by caching only those instructions whose instruction fetch phase collides with the memory access phase of a preceding load or store instruction. <p>Many existing machines provide a single cycle external cache memory. Our results show that, under this assumption, the stall cache always outperforms an equivalent sized on-chip instruction cache, reducing external memory access stalls by approximately 10%. In addition we present results for a system using an on-chip data cache, and for one with a double width data bus and short instruction prefetch buffer.

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BibTeX citation:

@techreport{Schauser:CSD-91-641,
    Author= {Schauser, Klaus Erik and Asanović, Krste and Patterson, David A. and Frank, Edward H.},
    Title= {Evaluation of a "Stall" Cache: An Efficient Restricted On-chip Instruction Cache},
    Year= {1991},
    Month= {Jul},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1991/6391.html},
    Number= {UCB/CSD-91-641},
    Abstract= {In this report we compare the cost and performance of a new kind of restricted instruction cache architecture -- the stall cache -- against several other conventional cache architectures. The stall cache minimizes the size of an on-chip instruction cache by caching only those instructions whose instruction fetch phase collides with the memory access phase of a preceding load or store instruction. <p>Many existing machines provide a single cycle external cache memory. Our results show that, under this assumption, the stall cache always outperforms an equivalent sized on-chip instruction cache, reducing external memory access stalls by approximately 10%. In addition we present results for a system using an on-chip data cache, and for one with a double width data bus and short instruction prefetch buffer.},
}

EndNote citation:

%0 Report
%A Schauser, Klaus Erik 
%A Asanović, Krste 
%A Patterson, David A. 
%A Frank, Edward H. 
%T Evaluation of a "Stall" Cache: An Efficient Restricted On-chip Instruction Cache
%I EECS Department, University of California, Berkeley
%D 1991
%@ UCB/CSD-91-641
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1991/6391.html
%F Schauser:CSD-91-641