SIS: A System for Sequential Circuit Synthesis

E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M92/41
May 1992

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1992/ERL-92-41.pdf

SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logic-level description of a sequential circuit, it produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared, and as a tool for automatic synthesis and optimization of sequential circuits. This paper provides an overview of SIS. The first part contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGA's (programmable gate arrays). The second part contains a tutorial example illustrating the design process using SIS.

BibTeX citation:

@techreport{Sentovich:M92/41,
    Author = {Sentovich, E.M. and Singh, K.J. and Lavagno, L. and Moon, C. and Murgai, R. and Saldanha, A. and Savoj, H. and Stephan, P.R. and Brayton, Robert K. and Sangiovanni-Vincentelli, Alberto L.},
    Title = {SIS: A System for Sequential Circuit Synthesis},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1992},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1992/2010.html},
    Number = {UCB/ERL M92/41},
    Abstract = {SIS is an interactive tool for synthesis and optimization of
sequential circuits. Given a state transition table, a signal
transition graph, or a logic-level description of a sequential
circuit, it produces an optimized net-list in the target technology
while preserving the sequential input-output behavior. Many
different programs and algorithms have been integrated into SIS,
allowing the user to choose among a variety of techniques at each
stage of the process. It is built on top of MISII and includes
all (combinational) optimization techniques therein as well as many
enhancements.  SIS serves as both a framework within which various
algorithms can be tested and compared, and as a tool for automatic
synthesis and optimization of sequential circuits. This paper
provides an overview of SIS. The first part contains descriptions of
the input specification, STG (state transition graph) manipulation,
new logic optimization and verification algorithms, ASTG
(asynchronous signal transition graph) manipulation, and synthesis
for PGA's (programmable gate arrays). The second part contains a
tutorial example illustrating the design process using SIS.}
}

EndNote citation:

%0 Report
%A Sentovich, E.M.
%A Singh, K.J.
%A Lavagno, L.
%A Moon, C.
%A Murgai, R.
%A Saldanha, A.
%A Savoj, H.
%A Stephan, P.R.
%A Brayton, Robert K.
%A Sangiovanni-Vincentelli, Alberto L.
%T SIS: A System for Sequential Circuit Synthesis
%I EECS Department, University of California, Berkeley
%D 1992
%@ UCB/ERL M92/41
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1992/2010.html
%F Sentovich:M92/41