P.R. Stephan and Robert K. Brayton

EECS Department, University of California, Berkeley

Technical Report No. UCB/ERL M93/33

, 1993

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/ERL-93-33.pdf

We propose an objective criterion for determining if, given a specific circuit technology, a gate model is suitable for synthesis and verification. This is based on relating the analog circuit behavior to the digital model behavior using a formal definition of implementation. We show how the criterion is not satisfied for several gate models currently used for synthesizing asynchronous circuits, and illustrate the design errors which occur when these models are used. Finally we introduce a new gate model which is designed to satisfy the criterion.

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BibTeX citation:

@techreport{Stephan:M93/33,
    Author= {Stephan, P.R. and Brayton, Robert K.},
    Title= {Physically Realizable Gate Models},
    Year= {1993},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2336.html},
    Number= {UCB/ERL M93/33},
    Abstract= {We propose an objective criterion for determining if, given a specific circuit technology, a gate model is suitable for synthesis and verification. This is based on relating the analog circuit behavior to the digital model behavior using a formal definition of implementation. We show how the criterion is not satisfied for several gate models currently used for synthesizing asynchronous circuits, and illustrate the design errors which occur when these models are used. Finally we introduce a new gate  model which is designed to satisfy the criterion.},
}

EndNote citation:

%0 Report
%A Stephan, P.R. 
%A Brayton, Robert K. 
%T Physically Realizable Gate Models
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/33
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2336.html
%F Stephan:M93/33