Exact Minimum Delay Computation and Clock Frequencies

W.K.C. Lam, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M93/40
May 1993

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/ERL-93-40.pdf

Minimum as well as maximum circuit delays play vital roles in high performance systems. In this paper, we analyze existing and new minimum delay models and show that these models are special cases of a general circuit delay model introduced in [LBSV92a] which also unifies all maximum delay models. Then, we provide algorithms to compute exactly various minimum circuit delays with arbitrary gate delay models under the same framework. Thus, all minimum and maximum circuit delay models are u unified and their corresponding delays can be computed exactly. Further, we consider the interactions of various minimum and maximum delays with clock frequencies of circuits. Finally, we provide experimental results on ISCAS benchmarks.

BibTeX citation:

@techreport{Lam:M93/40,
    Author = {Lam, W.K.C. and Brayton, Robert K. and Sangiovanni-Vincentelli, Alberto L.},
    Title = {Exact Minimum Delay Computation and Clock Frequencies},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1993},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2350.html},
    Number = {UCB/ERL M93/40},
    Abstract = {Minimum as well as maximum circuit delays play vital roles in high performance systems. In this paper, we analyze existing and new minimum delay models and show that these models are special cases of a general circuit delay model introduced in [LBSV92a] which also unifies all maximum delay models. Then, we provide algorithms to compute exactly various minimum circuit delays with arbitrary gate delay models under the same framework. Thus, all minimum and maximum circuit delay models are u unified and their corresponding delays can be computed exactly. Further, we consider the interactions of various minimum and maximum delays with clock frequencies of circuits. Finally, we provide experimental results on ISCAS benchmarks.}
}

EndNote citation:

%0 Report
%A Lam, W.K.C.
%A Brayton, Robert K.
%A Sangiovanni-Vincentelli, Alberto L.
%T Exact Minimum Delay Computation and Clock Frequencies
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/40
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2350.html
%F Lam:M93/40