A VLSI Design Methodology Using a Network of PLAs Embedded in a Regular Layout Fabric

S.P. Khatri, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M99/50
May 1999

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1999/ERL-99-50.pdf

BibTeX citation:

@techreport{Khatri:M99/50,
    Author = {Khatri, S.P. and Brayton, Robert K. and Sangiovanni-Vincentelli, Alberto L.},
    Title = {A VLSI Design Methodology Using a Network of PLAs Embedded in a Regular Layout Fabric},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1999},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1999/3747.html},
    Number = {UCB/ERL M99/50}
}

EndNote citation:

%0 Report
%A Khatri, S.P.
%A Brayton, Robert K.
%A Sangiovanni-Vincentelli, Alberto L.
%T A VLSI Design Methodology Using a Network of PLAs Embedded in a Regular Layout Fabric
%I EECS Department, University of California, Berkeley
%D 1999
%@ UCB/ERL M99/50
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1999/3747.html
%F Khatri:M99/50