John Wawrzynek and Mark Oskin and Christoforos Kozyrakis and Derek Chiou and David A. Patterson and Shih-Lien Lu and James C. Hoe and Krste Asanović

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2006-158

November 24, 2006

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-158.pdf

The Research Accelerator for Multiple Processors (RAMP) is an affordable and versatile multiprocessor emulation platform being built as a large collaborative effort. RAMP hardware, from processors to coherent caches to networks, is implemented in field-programmable gate arrays (FPGAs) for flexibility, accuracy, visibility, cost and performance. It is designed to be composable, where different components can be quickly written, collected, assembled and run. By using hardware rather than simulation, RAMP is fast enough to run real codes and be useful to software. By using conventional instruction set architectures and providing peripheral support required by operating systems, RAMP runs full, unmodified software stacks. RAMP's intended audience includes anyone designing and using multiprocessor systems including architects, designer, software developers and users. This paper introduces the RAMP vision and highlights the key current developments in the RAMP project including the RAMP Design Framework and three reference designs.

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BibTeX citation:

@techreport{Wawrzynek:EECS-2006-158,
    Author= {Wawrzynek, John and Oskin, Mark and Kozyrakis, Christoforos and Chiou, Derek and Patterson, David A. and Lu, Shih-Lien and Hoe, James C. and Asanović, Krste},
    Title= {RAMP: A Research Accelerator for Multiple Processors},
    Year= {2006},
    Month= {Nov},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-158.html},
    Number= {UCB/EECS-2006-158},
    Abstract= {The Research Accelerator for Multiple Processors (RAMP) is an affordable and versatile multiprocessor emulation platform being built as a large collaborative effort.  RAMP hardware, from processors to coherent caches to networks, is implemented in field-programmable gate arrays (FPGAs) for flexibility, accuracy, visibility, cost and performance.  It is designed to be composable, where different components can be quickly written, collected, assembled and run.  By using hardware rather than simulation, RAMP is fast enough to run real codes and be useful to software.  By using conventional instruction set architectures and providing peripheral support required by operating systems, RAMP runs full, unmodified software stacks.  RAMP's intended audience includes anyone designing and using multiprocessor systems including architects, designer, software developers and users. This paper introduces the RAMP vision and highlights the key current developments in the RAMP project including the RAMP Design Framework and  three reference designs.},
}

EndNote citation:

%0 Report
%A Wawrzynek, John 
%A Oskin, Mark 
%A Kozyrakis, Christoforos 
%A Chiou, Derek 
%A Patterson, David A. 
%A Lu, Shih-Lien 
%A Hoe, James C. 
%A Asanović, Krste 
%T RAMP: A Research Accelerator for Multiple Processors
%I EECS Department, University of California, Berkeley
%D 2006
%8 November 24
%@ UCB/EECS-2006-158
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-158.html
%F Wawrzynek:EECS-2006-158