Catalog Description: Instruction set architecture, microcoding, pipelining (simple and complex). Memory hierarchies and virtual memory. Processor parallelism: VLIW, vectors, multithreading. Multiprocessors.

Units: 4

Prerequisites: COMPSCI 61C

Formats:
Spring: 3.0 hours of lecture and 2.0 hours of discussion per week
Summer: 6.0 hours of lecture and 4.0 hours of discussion per week
Fall: 3.0 hours of lecture and 2.0 hours of discussion per week

Grading basis: letter

Final exam status: Alternative method of final assessment

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Class Schedule (Spring 2025):
CS 152/252A – TuTh 11:00-12:29, Physics Building 4 – Christopher Fletcher

Class homepage on inst.eecs

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Department Notes:

Course objectives: This course will give you an in-depth understanding of the inner-workings of modern digital computer systems and tradeoffs present at the hardware-software interface. You will work in groups of 4 or 5 to get an understanding of the design process in the context of a complex hardware system and practical experience with computer-aided design tools. You will be required to present your design and results in front of the TAs and class.

Topics covered:

• 5 components of a computer
• ISA's and Intro to MIPS
• MIPS operations and Performance
• Delay Modeling
• Low Power Design
• Design Process, ALU & Adders
• Multipliers & Shifters
• Dividers & Floating Point
• Verilog
• Design and testing methodologies
• Single cycle datapath and control
• Multiple cycle processor, controller, and microprogramming
• Exceptions
• Introduction to Pipelining
• Pipelining and control
• Pipelining and exceptions
• Advanced pipelining, Out-of-Order Execution, Branch Prediction
• Intro to Memory Systems
• Cache Design
• Virtual memory
• I/O Systems
• Embedded Processors
• DSP processors
• Real world processor design with examples of impact of technology

Related Areas:

• Computer Architecture & Engineering (ARC)