EE 219B. Logic Synthesis
Catalog Description: The course covers the fundamental techniques for the design and analysis of digital circuits. The goal is to provide a detailed understanding of basic logic synthesis and analysis algorithms, and to enable students to apply this knowledge in the design of digital systems and EDA tools. The course will present combinational circuit optimization (two-level and multi-level synthesis), sequential circuit optimization (state encoding, retiming), timing analysis, testing, and logic verification.
Units: 4
Prerequisites: Consent of instructor.
Formats:
Fall: 3 hours of lecture and 1 hour of discussion per week
Spring: 3 hours of lecture and 1 hour of discussion per week
Grading basis: letter
Final exam status: No final exam