Catalog Description: This lab lays the foundation of modern digital design by first presenting the scripting and hardware description language base for specification of digital systems and interactions with tool flows. The labs are centered on a large design with the focus on rapid design space exploration. The lab exercises culminate with a project design, e.g., implementation of a three-stage RISC-V processor with a register file and caches. The design is mapped to simulation and layout specification.

Units: 2

Course Objectives: Software testing of digital designs is covered leading to a set of exercises that cover the design flow. Digital synthesis, floor-planning, placement and routing are covered, as well as tools to evaluate timing and power consumption. Chip-level assembly is covered, including instantiation of custom blocks: I/O pads, memories, PLLs, etc.

Prerequisites: COMPSCI 61C, EECS 16A, EECS 16B, and EL ENG 105.

Formats:
Fall: 3.0 hours of laboratory per week

Grading basis: letter

Final exam status: No final exam

---

Class Schedule (Fall 2024):
EECS 151LA/251LA-101 – Mo 17:00-19:59, Cory 111 – Christopher Fletcher
EECS 151LA-2/251LA-102 – Th 14:00-16:59, Cory 111 – Christopher Fletcher
EECS 151LA-3/251LA-103 – Fr 11:00-13:59, Cory 111 – Christopher Fletcher
EECS 151LA-4/251LA-104 – Mo 11:00-13:59, Cory 111 – Christopher Fletcher
EECS 151LA-5/251LA-105 – Fr 17:00-19:59, Cory 111 – Christopher Fletcher

Class Schedule (Spring 2025):
EECS 151LA-101/251LA-101 – Tu 11:00-13:59, Cory 111 – John Wawrzynek
EECS 151LA-102/251LA-102 – Tu 14:00-16:59, Cory 111 – John Wawrzynek

Class homepage on inst.eecs