EECS 151LB. Field-Programmable Gate Array Laboratory

Catalog Description: This lab covers the design of modern digital systems with Field-Programmable Gate Array (FPGA) platforms. A series of lab exercises provide the background and practice of digital design using a modern FPGA design tool flow. Digital synthesis, partitioning, placement, routing, and simulation tools for FPGAs are covered in detail. The labs exercises culminate with a large design project, e.g., an implementation of a full three-stage RISC-V processor system, with caches, graphics acceleration, and external peripheral components. The design is mapped and demonstrated on an FPGA hardware platform.

Units: 2

Prerequisites: EECS 16A, EECS 16B, and COMPSCI 61C; EL ENG 105 recommended.

Spring: 3.0 hours of laboratory per week

Grading basis: letter

Final exam status: No final exam

Class Schedule (Fall 2023):
EECS 151LB/251LB-101 – Tu 14:00-16:59, Cory 111 – Borivoje NIKOLIC
EECS 151LB-2/251LB-102 – We 08:00-10:59, Cory 111 – Borivoje NIKOLIC
EECS 151LB-3/251LB-103 – Fr 08:00-10:59, Cory 111 – Borivoje NIKOLIC

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