Catalog Description: An introduction to digital circuit and system design. The material provides a top-down view of the principles, components, and methodologies for large scale digital system design. The underlying CMOS devices and manufacturing technologies are introduced, but quickly abstracted to higher levels to focus the class on design of larger digital modules for both FPGAs (field programmable gate arrays) and ASICs (application specific integrated circuits). The class includes extensive use of industrial grade design automation and verification tools for assignments, labs, and projects.

Units: 3

Course Objectives: The Verilog hardware description language is introduced and used. Basic digital system design concepts, Boolean operations/combinational logic, sequential elements and finite-state-machines, are described. Design of larger building blocks such as arithmetic units, interconnection networks, input/output units, as well as memory design (SRAM, Caches, FIFOs) and integration are also covered. Parallelism, pipelining and other micro-architectural optimizations are introduced. A number of physical design issues visible at the architecture level are covered as well, such as interconnects, power, and reliability.

Student Learning Outcomes: Although the syllabus is the same as EECS151, the assignments and exams for EECS251A will have harder problems that test deeper understanding expected from a graduate level course.

Prerequisites: EECS 16A and EECS 16B; COMPSCI 61C; and recommended: EL ENG 105. Students must enroll concurrently in at least one the laboratory flavors EECS 251LA or EECS 251LB. Students wishing to take a second laboratory flavor next term can sign-up only for that laboratory section and receive a letter grade. The prerequisite for “Lab-only” enrollment that term will be EECS 251A from previous terms.

Credit Restrictions: Students must enroll concurrently in at least one the laboratory flavors Electrical Engineering and Computer Science 251LA or Electrical Engineering and Computer Science 251LB. Students wishing to take a second laboratory flavor next term can sign-up only for that laboratory section and receive a letter grade. The pre-requisite for “Lab-only” enrollment that term will be Electrical Engineering and Computer Science 251A from previous terms.

Formats:
Spring: 3.0 hours of lecture and 1.0 hours of discussion per week
Fall: 3.0 hours of lecture and 1.0 hours of discussion per week

Grading basis: letter

Final exam status: Written final exam conducted during the scheduled final exam period

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Class Schedule (Fall 2024):
EECS 151/251A – TuTh 09:30-10:59, Mulford 159 – Christopher Fletcher

Class Schedule (Spring 2025):
EECS 151/251A – TuTh 09:30-10:59, Soda 306 – John Wawrzynek

Class homepage on inst.eecs

Related Areas:

• Computer Architecture & Engineering (ARC)