Catalog Description: This lab covers the design of modern digital systems with Field-Programmable Gate Array (FPGA) platforms. A series of lab exercises provide the background and practice of digital design using a modern FPGA design tool flow. Digital synthesis, partitioning, placement, routing, and simulation tools for FPGAs are covered in detail. The labs exercises culminate with a large design project, e.g., an implementation of a full 3-stage RISC-V processor system, with caches, graphics acceleration, and external peripheral components. The design is mapped and demonstrated on an FPGA hardware platform.

Units: 2

Student Learning Outcomes: Although the syllabus is the same as EECS151LB, the assignments and exams for EECS251LB will have harder problems in labs and in the project that test deeper understanding expected from a graduate level course.

Prerequisites: EECS 16A, EECS 16B, and COMPSCI 61C; and EL ENG 105 is recommended.

Formats:
Fall: 3.0 hours of laboratory per week

Grading basis: letter

Final exam status: No final exam

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Class Schedule (Fall 2024):
EECS 151LB/251LB-101 – Tu 14:00-16:59, Cory 111 – Christopher Fletcher
EECS 151LB-2/251LB-102 – We 17:00-19:59, Cory 111 – Christopher Fletcher
EECS 151LB-3/251LB-103 – Fr 08:00-10:59, Cory 111 – Christopher Fletcher
EECS 151LB-5/251LB-105 – Th 17:00-19:59, Cory 111 – Christopher Fletcher

Class Schedule (Spring 2025):
EECS 151LB/251LB-101 – Th 11:00-13:59, Cory 111 – John Wawrzynek
EECS 151LB-3/251LB-103 – We 17:00-19:59, Cory 111 –
EECS 151LB-4/251LB-104 – We 14:00-16:59, Cory 111 –

Class homepage on inst.eecs