Catalog Description: This lab covers the design of modern digital systems with Field-Programmable Gate Array (FPGA) platforms. A series of lab exercises provide the background and practice of digital design using a modern FPGA design tool flow. Digital synthesis, partitioning, placement, routing, and simulation tools for FPGAs are covered in detail. The labs exercises culminate with a large design project, e.g., an implementation of a full 3-stage RISC-V processor system, with caches, graphics acceleration, and external peripheral components. The design is mapped and demonstrated on an FPGA hardware platform.
Units: 2.0
Student Learning Outcomes: Although the syllabus is the same as EECS151LB, the assignments and exams for EECS251LB will have harder problems in labs and in the project that test deeper understanding expected from a graduate level course.
Prerequisites: Electrical Engineering 16A & 16B; Computer Science 61C; and recommended: Electrical Engineering 105.
Formats:
Fall: 3.0 hours of laboratory per week
Grading basis: letter
Final exam status: No final exam
Class Schedule (Spring 2020):
Th 11:00AM - 1:59PM, Cory 125 –
John Wawrzynek, Quincy Huynh, Tan Nguyen
We 2:00PM - 4:59PM, Cory 125 –
John Wawrzynek, Quincy Huynh, Tan Nguyen
Class Schedule (Fall 2020):
Mo 8:00AM - 10:59AM, Cory 125 –
Sophia Shao
Th 5:00PM - 7:59PM, Cory 125 –
Sophia Shao
We 5:00PM - 7:59PM, Cory 125 –
Sophia Shao