Books

• A. Kuehlmann, Ed., The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design, Boston: Kluwer Academic Publishers, 2003.

Book chapters or sections

• A. Kuehlmann and J. Baumgartner, "Transformation-based verification using generalized retiming," in Lecture Notes in Computer Science: Computer Aided Verification, G. Berry, H. Comon, and A. Finkel, Eds., 2102 ed., London, UK: Springer-Verlag, 2001, pp. 104-117.

Articles in journals or magazines

• D. Chai and A. Kuehlmann, "A fast pseudo-Boolean constraint solver," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 305-317, March 2005.
• A. Kuehlmann, V. Paruthi, F. Krohm, and M. K. Ganai, "Robust Boolean reasoning for equivalence checking and functional property verification," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 12, pp. 1377-1394, Dec. 2002.
• A. Kuehlmann, A. Srinivasan, and D. P. LaPotin, "Verity - A formal verification program for custom CMOS circuits," IBM J. Research and Development, vol. 39, no. 1-2, pp. 149-165, Jan. 1995.

Articles in conference proceedings

• J. C. Rey, J. M. Rabaey, A. Kuehlmann, C. Conroy, I. Kawasaki, T. B. Tarim, and T. Vucurevich, "Next Generation Wireless-Multimedia Devices--Who Is Up for the Challenge? (Panel Session)," in Proc. 45th ACM/IEEE Design Automation Conf. (DAC 2008), New York, NY: The Association for Computing Machinery, Inc., 2008, pp. 353-354.
• S. Chatterjee, A. Mishchenko, R. K. Brayton, and A. Kuehlmann, "On resolution proofs for combinational equivalence," in Proc. 44th Annual ACM/IEEE Design Automation Conf. (DAC 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 600-605.
• Q. Zhu, N. Kitchen, A. Kuehlmann, and A. L. Sangiovanni-Vincentelli, "SAT sweeping with local observability don't-cares," in Proc. 43rd ACM/IEEE Design Automation Conf. (DAC 2006), New York, NY: The Association for Computing Machinery, Inc., 2006, pp. 229-234.
• Z. Wei, D. Chai, A. Kuehlmann, and A. R. Newton, "Fast Boolean matching with don't cares," in Proc. 2006 7th Intl. Symp. on Quality Electronic Design (ISQED '06), Los Alamitos, CA: IEEE Computer Society Press, 2006, pp. 6 pp..
• A. Kuehlmann, "Dynamic transition relation simplification for bounded property checking," in Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, Piscataway, NJ: IEEE Press, 2004, pp. 50-57.
• A. Kuehlmann and F. Krohm, "Equivalence checking using cuts and heaps," in Proc. 34th Design Automation Conf., New York, NY: ACM Press, 1997, pp. 263-268.
• D. P. Appenzeller and A. Kuehlmann, "Formal verification of a PowerPC microprocessor," in Proc. 1995 IEEE Intl. Conf. on Computer Design: VLSI in Computer and Processors, Los Alamitos, CA: IEEE Computer Society Press, 1995, pp. 79-84.
• A. Kuehlmann, D. I. Cheng, A. Srinivasan, and D. P. LaPotin, "Error diagnosis for transistor-level verification," in Proc. 31st ACM/IEE Conf. on Design Automation, New York, NY: ACM Press, 1994, pp. 218-224.

Technical Reports

• S. Khatri, S. Sinha, A. Kuehlmann, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "SPFD-Based Wire Removal in a Network of PLAs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/17, March 1999.

Patents

• M. Boshernitsan, A. Kuehlmann, S. McPeak, P. Chong, and T. Welp, "Static analysis of computer code to determine impact of change to a code component upon a dependent code component," U.S. Patent 9,032,376. May 2015.
• A. Kuehlmann, K. L. McMillan, and S. Sagiv, "General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software," U.S. Patent 8,862,439. Oct. 2014.
• A. Kuehlmann, K. L. McMillan, and S. Sagiv, "Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software," U.S. Patent 8,656,330. Feb. 2014.
• C. Albrecht, P. Chong, A. Kuehlmann, E. Sentovich, and R. Passerone, "Optimizing integrated circuit design through use of sequential timing information," U.S. Patent 8,589,845. Nov. 2013.
• A. Kuehlmann and X. Du, "Temporal decomposition for design and verification," U.S. Patent 8,413,090. April 2013.
• A. Kuehlmann and X. Du, "Temporal decomposition for design and verification," U.S. Patent 8,418,101. April 2013.
• C. Albrecht, P. Chong, A. Kuehlmann, E. Sentovich, and R. Passerone, "Reducing critical cycle delay in an integrated circuit design through use of sequential slack," U.S. Patent 8,307,316. June 2012.
• A. Kuehlmann and N. Kitchen, "System, methods and apparatus for generation of simulation stimulus," U.S. Patent 8,020,125. Sep. 2011.
• A. Kuehlmann and X. Du, "Temporal decomposition for design and verification," U.S. Patent 7,900,173. March 2011.
• C. Albrecht, P. Chong, A. Kuehlmann, E. Sentovich, and R. Passerone, "Reducing critical cycle delay in an integrated circuit design through use of sequential slack," U.S. Patent 7,913,210. March 2011.
• C. Albrecht, P. Chong, A. Kuehlmann, E. Sentovich, and R. Passerone, "Optimizing integrated circuit design through use of sequential timing information," U.S. Patent 7,743,354. June 2010.
• C. Albrecht, P. Chong, A. Kuehlmann, E. Sentovich, and R. Passerone, "Data path and placement optimization in an integrated circuit through use of sequential timing information," U.S. Patent 7,624,364. Nov. 2009.
• A. Kuehlmann and X. Du, "Temporal decomposition for design and verification," U.S. Patent 7,596,770. Sep. 2009.
• C. Albrecht, A. Kuehlmann, D. Seibert, and S. Richter, "Optimization of combinational logic synthesis through clock latency scheduling," U.S. Patent 7,559,040. July 2009.
• A. Kuehlmann, K. Ravindran, and E. Sentovich, "Multi-domain clock skew scheduling," U.S. Patent 7,296,246. Nov. 2007.
• J. R. Baumgartner, G. Janssen, A. Kuehlmann, V. Paruthi, and L. H. Trevillyan, "Framework for multiple-engine based verification tools for integrated circuits," U.S. Patent 6,698,003. Feb. 2004.
• M. K. Ganai, G. Janssen, F. K. Krohm, A. Kuehlmann, and V. Paruthi, "Method and system for equivalence-checking combinatorial circuits using iterative binary-decision-diagram sweeping and structural satisfiability analysis," U.S. Patent 6,473,884. Oct. 2002.
• A. Kuehlmann and F. K. Krohm, "Method for performing functional comparison of combinational circuits," U.S. Patent 6,035,107. March 2000.
• S. Kundu, A. Kuehlmann, and A. Srinivasan, "CMOS transistor network to gate level model extractor for simulation, verification and test generation," U.S. Patent 5,629,858. May 1997.
• A. Kuehlmann and T. Philipp, "Matrix style layout for integrated circuits," Sep. 1989.
• J. Priesnitz and A. Kuehlmann, "Sequential circuit with integrated text support," June 1989.
• A. Kuehlmann and S. Ritter, "Regular logic structure for CMOS gate array circuits," June 1988.
• S. Ritter, A. Kuehlmann, A. Vogt, and J. Priesnitz, "Regular layout structure for CMOS silicon-gate circuits," June 1987.