Faculty Publications - Vladimir Stojanovic

Articles in journals or magazines

  • O. Tanovic, A. Megretski, Y. Li, V. Stojanovic, and M. Osqui, "Equivalent Baseband Models and Corresponding Digital Predistortion for Compensating Dynamic Passband Nonlinearities in Phase-Amplitude Modulation-Demodulation Schemes," IEEE Transactions on Signal Processing, vol. 66, no. 22, pp. 5972-5987, 2018.
  • Y. Kang, J. Bokor, and V. Stojanovic, "Design Requirements for a Spintronic MTJ Logic Device for Pipelined Logic Applications," IEEE Transactions on Electron Devices, vol. 63, no. 4, pp. 1754--1761, 2016.
  • C. Sorace-Agaskar, J. Leu, M. R. Watts, and V. Stojanovic, "Electro-optical co-simulation for integrated CMOS photonic circuits with VerilogA," Opt. Express, vol. 23, no. 21, pp. 27180--27203, Oct. 2015.
  • A. Suleiman, R. Sredojevic, and V. Stojanovic, "Model Predictive Control Equalization for High-Speed I/O Links," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 2, pp. 371-381, 2014.
  • Y. Li, Z. Li, O. Uyar, Y. Avniel, A. Megretski, and V. Stojanovic, "High-Throughput Signal Component Separator for Asymmetric Multi-Level Outphasing Power Amplifiers," IEEE Journal of Solid-State Circuits, vol. 48, no. 2, pp. 369-380, 2013.
  • F. Lim and V. Stojanovic, "On U-Statistics and Compressed Sensing I: Non-Asymptotic Average-Case Analysis," IEEE Transactions on Signal Processing, vol. 61, no. 10, pp. 2473-2485, 2013.
  • F. Chen, F. Lim, O. Abari, A. Chandrakasan, and V. Stojanovic, "Energy-Aware Design of Compressed Sensing Systems for Wireless Sensors Under Performance and Reliability Constraints," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 3, pp. 650-661, 2013.
  • F. Lim and V. Stojanovic, "On U-Statistics and Compressed Sensing II: Non-Asymptotic Worst-Case Analysis," IEEE Transactions on Signal Processing, vol. 61, no. 10, pp. 2486-2497, 2013.
  • T. K. Liu, D. Markovic, V. Stojanovic, and E. Alon, "The relay reborn," IEEE Spectrum, vol. 49, no. 4, pp. 40-43, 2012.
  • M. Zhang, V. Stojanovic, and P. Ampadu, "Reliable Ultra-Low-Voltage Cache Design for Many-Core Systems," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 12, pp. 858-862, 2012.
  • S. D. Vamvakos, V. Stojanovic, and B. Nikolic, "Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 6, pp. 1211-1224, 2011.
  • N. Blitvic, M. Lee, and V. Stojanovic, "Channel Coding For High-Speed Links: A Systematic Look at Code Performance and System Simulation," IEEE Transactions on Advanced Packaging, vol. 32, no. 2, pp. 268-279, 2009.
  • C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, "Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics," IEEE Micro, vol. 29, no. 4, pp. 8-21, 2009.

Technical Reports

Patents

Ph.D. Theses

Masters Reports