Books

• T. El-Ghazawi, W. Carlson, T. Sterling, and K. A. Yelick, UPC: Distributed Shared-Memory Programming, Wiley-Interscience, Hoboken, NJ: Wiley, 2005.
• A. W. Trivelpiece, R. Biswas, J. Dongarra, P. Paul, and K. A. Yelick, Assessment of High-End Computing Research and Development in Japan: Final Report, Baltimore, MD: World Technology Evaluation Center, Inc., 2004.

Book chapters or sections

• J. Su and K. A. Yelick, "Automatic communication performance debugging in PGAS languages," in Languages and Compilers for Parallel Computing: Proc. 20th Intl. Workshop (LCPC 2007). Revised Selected Papers, V. Adve, M. J. Garzaran, and P. Petersen, Eds., Lecture Notes in Computer Science, Vol. 5234, Berlin, Germany: Springer-Verlag, 2008, pp. 232-245.
• A. Kamil and K. A. Yelick, "Hierarchical pointer analysis for distributed programs," in Static Analysis: Proc. 14th Intl. Symp. (SAS 2007), H. Riis Nielson and G. File, Eds., Lecture Notes in Computer Science, Vol. 4634, Berlin, Germany: Springer-Verlag, 2007, pp. 281-297.
• E. J. Im, I. Bustany, C. Ashcraft, J. Demmel, and K. A. Yelick, "Performance tuning of matrix triple products based on matrix structure," in Applied Parallel Computing: State of the Art in Scientific Computing. Proc. 7th Intl. Workshop (PARA 2004): Revised Selected Papers, J. Dongarra, K. Madsen, and J. Wasniewski, Eds., Lecture Notes in Computer Science, Vol. 3732, Berlin, Germany: Springer-Verlag, 2006, pp. 740-746.
• R. Vuduc, A. Gyulassy, J. Demmel, and K. A. Yelick, "Memory hierarchy optimizations and performance bounds for Sparse {A sup T Ax}," in Computational Science: Proc. Intl. Conf. on Computational Science (ICCS 2003), P. M. A. Sloot, D. Abramson, A. V. Bogdanov, J. J. Dongarra, A. Y. Zomaya, and Y. E. Gorbachev, Eds., Lecture Notes in Computer Science, Vol. 2659, Berlin, Germany: Springer-Verlag, 2003, pp. 705-714.

Articles in journals or magazines

• J. Chapman, M. Mascher, A. Buluç, K. Barry, E. Georganas, A. Session, V. Strnadova, J. Jenkins, S. Sehgal, L. Oliker, J. Schmutz, K. A. Yelick, U. Scholz, R. Waugh, J. Poland, G. Muehlbauer, N. Stein, and D. Rokhsar, "A whole-genome shotgun approach for assembling and anchoring the hexaploid bread wheat genome," Genome Biology, vol. 16, no. 26, 2015.
• J. Shalf, K. Asanović, D. A. Patterson, K. Keutzer, T. Mattson, and K. A. Yelick, "The Manycore Revolution: Will the HPC Community Lead or Follow?," SciDAC Review, pp. 40-49, 2009.
• K. Asanović, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, N. Morgan, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick, "A View of the Parallel Computing Landscape," Communications of the ACM, vol. 52, no. 10, pp. 56-67, Oct. 2009.
• K. A. Yelick, P. N. Hilfinger, S. L. Graham, D. Bonachea, J. Su, A. Kami, K. Datta, P. Colella, and T. Wen, "Parallel languages and compilers: Perspective from the Titanium experience," Intl. J. High Performance Computing Applications, vol. 21, no. 3, pp. 266-290, 2007.
• S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, and K. A. Yelick, "Scientific computing kernels on the cell processor," Intl. J. Parallel Programming, vol. 35, no. 3, pp. 263-398, June 2007.
• R. Nishtala, R. W. Vuduc, J. Demmel, and K. A. Yelick, "When cache blocking of sparse matrix vector multiply works and why," Applicable Algebra in Engineering, Communication and Computing, vol. 18, no. 3, pp. 297-311, May 2007.
• E. Lusk and K. A. Yelick, "Languages for high-productivity computing: The DARPA HPCS Language Project," Parallel Processing Letters, vol. 17, no. 1, pp. 89-102, March 2007.
• E. Givelberg and K. A. Yelick, "Distributed immersed boundary simulations in Titanium," SIAM J. on Scientific Computing, vol. 28, no. 4, pp. 1361-1378, July 2006.
• R. Vuduc, J. Demmel, and K. A. Yelick, "OSKI: A library of automatically tuned sparse matrix kernels," J. Physics: Conference Series, vol. 16, no. 1, pp. 521-530, 2005.
• J. Demmel, J. Dongarra, V. Eijkhout, E. Fuentes, A. Petitet, R. Vuduc, R. C. Whaley, and K. A. Yelick, "Self-adapting linear algebra algorithms and software," Proc. IEEE, vol. 93, no. 2, pp. 293-312, Feb. 2005.
• D. Oppenheimer, A. Brown, J. Beck, D. Hettena, J. Kuroda, N. Treuhaft, D. A. Patterson, and K. A. Yelick, "ROC-1: hardware support for recovery-oriented computing," IEEE Transactions on Computers, vol. 51, no. 2, pp. 100-107, Feb. 2002.
• C. Kozyrakis, D. Judd, J. Gebis, S. Williams, D. A. Patterson, and K. A. Yelick, "Hardware/compiler Codevelopment for an Embedded Media Processor," Proceedings of the IEEE, vol. 89, no. 11, pp. 1694-709, Nov. 2001.
• K. A. Yelick, L. Semenzato, G. Pike, C. Miyamoto, B. Liblit, A. Krishnamurthy, P. N. Hilfinger, S. L. Graham, D. Gay, P. Colella, and A. Aiken, "Titanium: A high-performance Java dialect," Concurrency: Practice and Experience, vol. 10, no. 11-13, pp. 825-836, Sep. 1998.
• S. Chakrabarti, J. Demmel, and K. A. Yelick, "Models and scheduling algorithms for mixed data and task parallel programs," J. Parallel and Distributed Computing: Special Issue on Dynamic Load Balancing, vol. 47, no. 1, pp. 168-184, Nov. 1997.
• C. Kozyrakis, S. Perissakis, D. A. Patterson, T. Anderson, K. Asanović, N. Cardwell, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, R. Thomas, N. Treuhaft, and K. A. Yelick, "Scalable Processors in the Billion Transistor: IRAM," Proceedings IEEE Computer, vol. 30, no. 9, Sep. 1997.
• D. A. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. A. Yelick, "A Case for Intelligent DRAM: IRAM," IEEE Micro, vol. 17, no. 2, pp. 34-44, March 1997.

Articles in conference proceedings

• A. Tripathy, K. A. Yelick, and A. Buluç, "Reducing Communication in Graph Neural Network Training," in Proceedings of the 2020 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis, SC'20, 2020.
• E. Georganas, R. Egan, S. Hofmeyr, E. Goltsman, B. Arndt, A. Tritt, A. Buluç, L. Oliker, and K. A. Yelick, "Extreme scale de novo metagenome assembly," in Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC'18), 2018, pp. 10.
• P. Koanantakool, A. Ali, A. Azad, A. Buluç, D. Morozov, S. Oh, L. Oliker, and K. A. Yelick, "Communication-Avoiding Optimization Methods for Distributed Massive-Scale Sparse Inverse Covariance Estimation," in The 21st International Conference on Artificial Intelligence and Statistics (AISTATS), 2018.
• E. Georganas, A. Buluç, J. Chapman, L. Oliker, D. Rokhsar, and K. A. Yelick, "Parallel de bruijn graph construction and traversal for de novo genome assembly," in Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2014, pp. 437--448.
• P. Koanantakool and K. A. Yelick, "A Computation- and Communication-optimal Parallel Direct 3-body Algorithm," in Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC '14, Piscataway, NJ, USA: IEEE Press, 2014, pp. 363--374.
• M. Driscoll, E. Georganas, P. Koanantakool, E. Solomonik, and K. A. Yelick, "A communication-optimal N-body algorithm for direct interactions," in Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), 2013.
• E. Georganas, J. Gonz{citeKey, \'a}lez-Dom{\'\i, E. Solomonik, Y. Zheng, J. Touri{\~n}o, and K. A. Yelick, "Communication Avoiding and Overlapping for Numerical Linear Algebra," in SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis (Supercomputing 2012), 2012.
• B. C. Catanzaro, S. A. Kamil, Y. Lee, K. Asanović, J. Demmel, K. Keutzer, J. Shalf, K. A. Yelick, and A. Fox, "SEJITS: Getting productivity and performance with selective embedded JIT specialization," in Proceedings First Workshop on Programming Models for Emerging Architectures, 2009.
• K. Datta, M. Murphy, V. Volkov, S. Williams, J. Carter, L. Oliker, D. A. Patterson, J. Shalf, and K. A. Yelick, "Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures," in Proc. 2008 ACM/IEEE Conf. on Supercomputing (SC '08), Piscataway, NJ: IEEE Press, 2008, pp. Art. 4.
• C. Iancu, W. Chen, and K. A. Yelick, "Performance portable optimizations for loops containing communication operations," in Proc. 22nd Annual Intl. Conf. on Supercomputing (ICS 2008), New York, NY: The Association for Computing Machinery, Inc., 2008, pp. 266-276.
• S. Williams, J. Carter, L. Oliker, J. Shalf, and K. A. Yelick, "Lattice Boltzmann simulation optimization on leading multicore platforms," in Proc. 22nd IEEE Intl. Parallel & Distributed Processing Symp. (IPDPS 2008), Piscataway, NJ: IEEE Press, 2008, pp. 14 pg.
• K. A. Yelick, "Programming Models for Petascale to Exascale (Keynote Address)," in Proc. 22nd IEEE Intl. Parallel & Distributed Processing Symp. (IPDPS 2008), Piscataway, NJ: IEEE Press, 2008, pp. 1 pg.
• J. Demmel, M. Hoemmen, M. Hohiyuddin, and K. A. Yelick, "Avoiding communication in sparse matrix computations," in Proc. 22nd IEEE Intl. Parallel & Distributed Processing Symp. (IPDPS 2008), Piscataway, NJ: IEEE Press, 2008, pp. 12 pg.
• P. Husbands and K. A. Yelick, "Multi-threading and one-sided communication in parallel LU factorization," in Proc. 2007 ACM/IEEE Conf. on Supercomputing (SC '07), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. Art. 31.
• S. Williams, L. Oliker, R. Vuduc, J. Shalf, K. A. Yelick, and J. Demmel, "Optimization of sparse matrix-vector multiplication on emerging multicore platforms," in Proc. 2007 ACM/IEEE Conf. on Supercomputing (SC '07), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. Art. 38.
• T. Wen, J. Su, P. Colella, K. A. Yelick, and N. Keen, "An adaptive mesh refinement benchmark for modern parallel programming languages," in Proc. 2007 ACM/IEEE Conf. on Supercomputing (SC '07), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. Art. 40.
• C. Iancu, W. Chen, and K. A. Yelick, "Performance portable optimizations for loops containing communication operations," in Proc. 16th Intl. Conf. on Parallel Architecture and Compilation Techniques (PACT 2007), Los Alamitos, CA: IEEE Computer Society, 2007, pp. 411-411.
• K. A. Yelick, D. Bonachea, W. Y. Chen, P. Colella, K. Datta, J. Duell, S. L. Graham, P. Hargrove, P. N. Hilfinger, P. Husbands, C. Iancu, A. Kamil, R. Nishtala, J. Su, M. Welcome, and T. Wen, "Productivity and performance using partitioned global address space languages (Invited Paper)," in Proc. 2007 Intl. Workshop on Parallel Symbolic Computation (PASCO '07), M. M. Maza and S. M. Watt, Eds., New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 24-32.
• S. Agarwal, R. Barik, D. Bonachea, V. Sarkar, R. K. Shyamasundar, and K. A. Yelick, "Deadlock-free scheduling of X10 computations with bounded resources," in Proc. 19th Annual ACM Symp. on Parallelism in Algorithms and Architectures (SPAA 2007), New York,NY: The Association for Computing Machinery, Inc., 2007, pp. 229-240.
• W. Y. Chen, D. Bonachea, C. Iancu, and K. A. Yelick, "Automatic nonblocking communication for partitioned global address space programs," in Proc. 21st Annual Intl. Conf. on Supercomputing (ICS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 158-167.
• H. Gahvari, M. Hoemmen, J. Demmel, and K. A. Yelick, "Benchmarking sparse matrix-vector multiply in five minutes," in Proc. 2007 SPEC Benchmark Workshop, Warrenton, VA: Standard Performance Evaluation Corporation, 2007, pp. 11 pg.
• S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, and K. A. Yelick, "The potential of the Cell processor for scientific computing," in Proc. 3rd Conf. on Computing Frontiers, New York, NY: ACM Press, 2006, pp. 9-20.
• C. Bell, D. Bonachea, R. Nishtala, and K. A. Yelick, "Optimizing bandwidth limited problems using one-sided communication and overlap," in Proc. 20th Intl. Parallel and Distributed Processing Symp., Piscataway, NJ: IEEE Press, 2006, pp. 10 pp..
• A. Kamil, J. Su, and K. A. Yelick, "Making sequential consistency practical in Titanium," in Proc. 2005 ACM/IEEE Supercomputing Conf., Los Alamitos, CA: IEEE Computer Society Press, 2005, pp. 15 pp..
• B. C. Lee, R. W. Vuduc, J. Demmel, and K. A. Yelick, "Performance models for evaluation and automatic tuning of symmetric sparse matrix-vector multiply (Best Paper Prize)," in Proc. 2004 Intl. Conf. on Parallel Processing (ICPP 2004), R. Eigenmann, Ed., Vol. 1, Los Alamitos, CA: IEEE Computer Society, 2004, pp. 169-176.
• W. Chen, D. Bonachea, J. Duell, P. Husbands, C. Iancu, and K. A. Yelick, "A performance analysis of the Berkeley UPC compiler," in Proc. 17th Annual Intl. Conf. on Supercomputing, New York, NY: ACM Press, 2003, pp. 63-73.
• R. Vuduc, J. Demmel, K. A. Yelick, S. Kamil, R. Nishtala, and B. Lee, "Performance optimizations and bounds for sparse matrix-vector multiply," in Proc. ACM/IEEE 2002 Conf. on Supercomputing (SC '02), Los Alamitos,CA: IEEE Computer Society, 2002, pp. 35 pg.
• B. R. Gaeke, P. Husbands, X. S. Li, L. Oliker, K. A. Yelick, and R. Biswas, "Memory-intensive benchmarks: IRAM vs. cache-based machines," in Proc. 16th Intl. Parallel and Distributed Processing Symp., Piscataway, NJ: IEEE Press, 2002, pp. 30-36.
• D. Judd, K. A. Yelick, C. Kozyraki, D. Martin, and D. A. Patterson, "Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler," in Revised Papers from the Second International Workshop on Intelligent Memory Systems, IMS, London, UK: Springer-Verlag, 2000, pp. 122 - 134.
• C. Kozyrakis, J. Gebis, D. Martin, S. Williams, I. Mavroidis, S. Pope, D. Jones, D. A. Patterson, and K. A. Yelick, "Vector IRAM: A Media-oriented Vector Processor with Embedded DRAM," in Proceedings of the 12th Hot Chips Conference, 2000.
• R. H. Arpaci-Dusseau, E. Anderson, N. Treuhaft, D. E. Culler, J. M. Hellerstein, D. A. Patterson, and K. A. Yelick, "Cluster I/O with River: Making the fast case common," in Proc. 6th Workshop on I/O in Parallel and Distributed Systems (IOPADS 1999), New York, NY: ACM Press, 1999, pp. 10-22.
• D. A. Patterson, K. Asanović, A. Brown, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, C. Kozyrakis, D. Martin, S. Perissakis, R. Thomas, N. Treuhaft, and K. A. Yelick, "Intelligent RAM (IRAM): The Industrial Setting, Applications, and Architectures," in Proceedings of ICCD ‘97 International Conference on Computer Design: VLSI in Computers and Processors, ICCD, IEEE, 1997, pp. 2 - 7.
• R. Fromm, S. Perissakis, N. Cardwell, C. Kozyrakis, B. McGaughy, D. A. Patterson, T. Anderson, and K. A. Yelick, "The Energy Efficiency of IRAM Architectures," in Proceedings of the 24th annual international symposium on Computer architecture, ACM SIGARCH Computer Architecture News, Vol. 25, New York, NY: ACM, 1997, pp. 327-337.
• D. A. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. A. Yelick, "Intelligent RAM (IRAM): Chips that Remember and Compute," in Digest of Technical Papers, ISSCC, New York, NY: IEEE, 1997, pp. 224 - 225.

Technical Documentation

• P. N. Hilfinger, D. Bonachea, K. Datta, D. Gay, S. L. Graham, A. Kamil, B. Liblit, G. Pike, J. Su, and K. A. Yelick, "Titanium Language Reference Manual (Version 2.20)," 2006.

Technical Reports

• M. Christ, J. Demmel, N. Knight, T. Scanlon, and K. A. Yelick, "Communication Lower Bounds and Optimal Algorithms for Programs That Reference Arrays - Part 1," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2013-61, May 2013.
• J. Byun, R. Lin, K. A. Yelick, and J. Demmel, "Autotuning Sparse Matrix-Vector Multiplication for Multicore," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2012-215, Nov. 2012.
• E. Georganas, J. González-Domínguez, E. Solomonik, Y. Zheng, J. Touriño, and K. A. Yelick, "Communication Avoiding and Overlapping for Numerical Linear Algebra," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2012-65, May 2012.
• A. A. Kamil and K. A. Yelick, "Hierarchical Additions to the SPMD Programming Model," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2012-20, Feb. 2012.
• B. Catanzaro, S. A. Kamil, Y. Lee, K. Asanović, J. Demmel, K. Keutzer, J. Shalf, K. A. Yelick, and A. Fox, "SEJITS: Getting Productivity and Performance With Selective Embedded JIT Specialization," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2010-23, March 2010.
• K. Asanović, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, E. A. Lee, N. Morgan, G. Necula, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick, "The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-23, March 2008.
• J. Demmel, M. F. Hoemmen, M. Mohiyuddin, and K. A. Yelick, "Avoiding Communication in Computing Krylov Subspaces," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2007-123, Oct. 2007.
• K. Asanović, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The Landscape of Parallel Computing Research: A View from Berkeley," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-183, Dec. 2006.
• J. Z. Su, T. Wen, and K. A. Yelick, "Compiler and Runtime Support for Scaling Adaptive Mesh Refinement Computations in Titanium," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-87, June 2006.
• A. A. Kamil and K. A. Yelick, "Concurrency Analysis for Parallel Programs with Textually Aligned Barriers," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-41, April 2006.
• P. N. Hilfinger, D. O. Bonachea, K. Datta, D. Gay, S. L. Graham, B. R. Liblit, G. Pike, J. Z. Su, and K. A. Yelick, "Titanium Language Reference Manual, version 2.19," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2005-15, Nov. 2005.
• R. Nishtala, R. W. Vuduc, J. W. Demmel, and K. A. Yelick, "Performance Modeling and Analysis of Cache Blocking in Sparse Matrix Vector Multiply," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-04-1335, 2004.
• B. C. Lee, R. W. Vuduc, J. W. Demmel, K. A. Yelick, M. de Lorimier, and L. Zhong, "Performance Optimizations and Bounds for Sparse Symmetric Matrix-Multiple Vector Multiply," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-03-1297, 2003.
• M. Narayanan and K. A. Yelick, "Generating Permutation Instructions from a High-Level Description," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-03-1287, 2003.
• W. Chen, A. Krishnamurthy, and K. Yelick, "Polynomial-time Algorithms for Enforcing Sequential Consistency for SPMD Programs with Arrays," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-03-1272, Sep. 2003.
• R. Vuduc, A. Gyulassy, J. Demmel, and K. A. Yelick, "Memory Hierarchy Optimizations and Performance Bounds for Sparse A^T Ax," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-03-1232, Feb. 2003.
• P. N. Hilfinger, D. Bonachea, D. Gay, S. Graham, B. Liblit, G. Pike, and K. Yelick, "Titanium Language Reference Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-01-1163, Nov. 2001.
• B. Liblit, A. Aiken, and K. Yelick, "Data Sharing Analysis for Titanium," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-01-1165, Nov. 2001.
• A. Krishnamurthy, D. E. Culler, and K. Yelick, "Empirical Evaluation of Global Memory Support on the Cray-T3D and Cray-T3E," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-98-991, Aug. 1998.
• A. Krishnamurthy, K. E. Schauser, C. J. Scheiman, D. E. Culler, K. Yelick, and R. Y. Wang, "Evaluation of Architectural Support for Global Address-Based Communication in Large-Scale Parallel Machines," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-98-984, Jan. 1998.
• S. Chakrabarti, E. Deprit, E. Im, J. Jones, A. Krishnamurthy, C. Wen, and K. Yelick, "Multipol: A Distributed Data Structure Library," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-95-879, July 1995.

Software

• K. A. Yelick and J. Demmel, "OSKI -- Optimized Sparse Kernel Interface," 2006.
• E. Givelberg and K. A. Yelick, "IB Using Titanium," 2005.
• K. A. Yelick, P. N. Hilfinger, S. L. Graham, and P. Colella, "The Titanium Compiler," 2003.
• W. Chen, D. Bonachea, J. Duell, P. Husbands, C. Iancu, K. A. Yelick, and D. E. Culler, "The Berkeley UPC Compiler," 2003.

Ph.D. Theses

• M. Ellis, "Parallelizing Irregular Applications for Distributed Memory Scalability: Case Studies from Genomics," K. A. Yelick, J. Demmel, A. Buluç, and D. Rokhsar, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2020-133, June 2020.

Masters Reports

• U. Mukhopadhyay, "Sparsity-aware communication for distributed graph neural network training," K. A. Yelick and A. Buluç, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2023-253, Dec. 2023.
• M. Driscoll, "Subdivision Surface Evaluation as Sparse Matrix-Vector Multiplication," K. A. Yelick and A. Fox, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-231, Dec. 2014.

Miscellaneous

• K. A. Yelick and M. Ellis, "merBench: PGAS Benchmarks for High Performance Genome Assembly," 2017.