Randy H. Katz, David A. Wood, Susan J. Eggers, Charles Perkins and Robert G. Sheldon

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-84-207
October 1984

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1984/CSD-84-207.pdf

We present an ownership-based multiprocessor cache consistency protocol, designed for implementation by a single chip VLSI cache controller. The protocol and its VLSI realization are described in some detail, to emphasize the important implementation issues, in particular, the controller critical sections and the inter- and intra-cache interlocks needed to maintain cache consistency. The design has been carried through to layout in a P-Well CMOS technology.

BibTeX citation:

@techreport{Katz:CSD-84-207,
    Author = {Katz, Randy H. and Wood, David A. and Eggers, Susan J. and Perkins, Charles and Sheldon, Robert G.},
    Title = {Implementing a Cache Consistency Protocol},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1984},
    Month = {Oct},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1984/5945.html},
    Number = {UCB/CSD-84-207},
    Abstract = {We present an ownership-based multiprocessor cache consistency protocol, designed for implementation by a single chip VLSI cache controller. The protocol and its VLSI realization are described in some detail, to emphasize the important implementation issues, in particular, the controller critical sections and the inter- and intra-cache interlocks needed to maintain cache consistency.  The design has been carried through to layout in a P-Well CMOS technology.}
}

EndNote citation:

%0 Report
%A Katz, Randy H.
%A Wood, David A.
%A Eggers, Susan J.
%A Perkins, Charles
%A Sheldon, Robert G.
%T Implementing a Cache Consistency Protocol
%I EECS Department, University of California, Berkeley
%D 1984
%@ UCB/CSD-84-207
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1984/5945.html
%F Katz:CSD-84-207