Jonathan Pincus

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-86-285

, 1986

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/CSD-86-285.pdf

Several methods of choosing appropriate sizes for transistors in a VLSI schematic to meet a specified delay criteria are considered. Simulated annealing and heuristic techniques are investigated. MOST is a Prolog program which makes use of information provided by the PTA timing analyzer to implement these various approaches. Both MOST and PTA are written entirely in (interpreted) Prolog; nonetheless, performance gains of over 50% as compared to an unsized circuit can be realized in a few minutes of CPU time. Using a simple RC timing model, heuristics are found to be more efficient than simulated annealing.

---

BibTeX citation:

@techreport{Pincus:CSD-86-285,
    Author= {Pincus, Jonathan},
    Title= {Transistor Sizing},
    Year= {1986},
    Month= {Feb},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/5375.html},
    Number= {UCB/CSD-86-285},
    Abstract= {Several methods of choosing appropriate sizes for transistors in a VLSI schematic to meet a specified delay criteria are considered. Simulated annealing and heuristic techniques are investigated. MOST is a Prolog program which makes use of information provided by the PTA timing analyzer to implement these various approaches. Both MOST and PTA are written entirely in (interpreted) Prolog; nonetheless, performance gains of over 50% as compared to an unsized circuit can be realized in a few minutes of CPU time. Using a simple RC timing model, heuristics are found to be more efficient than simulated annealing.},
}

EndNote citation:

%0 Report
%A Pincus, Jonathan 
%T Transistor Sizing
%I EECS Department, University of California, Berkeley
%D 1986
%@ UCB/CSD-86-285
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/5375.html
%F Pincus:CSD-86-285