Walter Stewart Scott

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-86-269

, 1986

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/CSD-86-269.pdf

Although the full-custom approach to the design of integrated circuits offers many advantages over other approaches, it is the most time-consuming design style of all. Much of this time is spent during the debug cycle, making changes to the layout of the circuit and then running a circuit extractor prior to simulating the design. This thesis introduces two new computer-aided design tools that drastically reduce the time spent in this debug cycle: a fast, new circuit extractor, and an operation called plowing for making changes to mask-level layout. Both tools have been implemented as part of the Magic IC layout system. <p> The circuit extractor is both incremental and hierarchical. It computes circuit connectivity and transistor dimensions, both internodal and substrate parasitic capacitance, and parasitic resistances. It is parameterized to work across a wide range of MOS technologies. The keys to its speed are a new mask-level extraction algorithm based on corner-stitching, and its ability to extract cells incrementally. The mask-level extractor is 3-5 times faster than the fastest previously published extractor, and computes significantly more information. Because the extractor is incremental, only a few cells must be re-extracted after typical changes to a layout. The above facts make it possible to re-extract incrementally a 36,000-transistor chip in under 10 minutes, an operation that used to take previous extractors hours to perform. <p> Plowing is a new operation for stretching and compacting parts of an IC layout. It allows designers to make topological changes to a layout while maintaining connectivity and layout rule correctness. Plowing can be used to rearrange the geometry of a subcell, compact a sparse layout, or open up new space in a dense layout. Unlike traditional compactors, plowing works directly on the mask-level representation of a layout. It uses a novel edge-based algorithm that works from a corner-stitched layout. This algorithm applies a collection of rules, parameterized by a technology file, to determine when edges must move.

Advisors: John K. Ousterhout

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BibTeX citation:

@phdthesis{Scott:CSD-86-269,
    Author= {Scott, Walter Stewart},
    Title= {Compaction and Circuit Extraction in the MAGIC IC Layout System},
    School= {EECS Department, University of California, Berkeley},
    Year= {1986},
    Month= {Nov},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/6087.html},
    Number= {UCB/CSD-86-269},
    Abstract= {Although the full-custom approach to the design of integrated circuits offers many advantages over other approaches, it is the most time-consuming design style of all. Much of this time is spent during the debug cycle, making changes to the layout of the circuit and then running a circuit extractor prior to simulating the design. This thesis introduces two new computer-aided design tools that drastically reduce the time spent in this debug cycle: a fast, new circuit extractor, and an operation called plowing for making changes to mask-level layout. Both tools have been implemented as part of the Magic IC layout system.  <p>  The circuit extractor is both incremental and hierarchical. It computes circuit connectivity and transistor dimensions, both internodal and substrate parasitic capacitance, and parasitic resistances. It is parameterized to work across a wide range of MOS technologies. The keys to its speed are a new mask-level extraction algorithm based on corner-stitching, and its ability to extract cells incrementally. The mask-level extractor is 3-5 times faster than the fastest previously published extractor, and computes significantly more information. Because the extractor is incremental, only a few cells must be re-extracted after typical changes to a layout. The above facts make it possible to re-extract incrementally a 36,000-transistor chip in under 10 minutes, an operation that used to take previous extractors hours to perform.  <p>  Plowing is a new operation for stretching and compacting parts of an IC layout. It allows designers to make topological changes to a layout while maintaining connectivity and layout rule correctness. Plowing can be used to rearrange the geometry of a subcell, compact a sparse layout, or open up new space in a dense layout. Unlike traditional compactors, plowing works directly on the mask-level representation of a layout. It uses a novel edge-based algorithm that works from a corner-stitched layout. This algorithm applies a collection of rules, parameterized by a technology file, to determine when edges must move.},
}

EndNote citation:

%0 Thesis
%A Scott, Walter Stewart 
%T Compaction and Circuit Extraction in the MAGIC IC Layout System
%I EECS Department, University of California, Berkeley
%D 1986
%@ UCB/CSD-86-269
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/6087.html
%F Scott:CSD-86-269