Belle W. Y. Wei and Clark D. Thompson and Yih-Farn Chen

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-86-252

, 1986

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/CSD-86-252.pdf

In this paper, we present a systematic method of implementing a VLSI parallel adder. First, we define a family of adders, based on a modular design. Our design uses three types of component cells, which we implement in static CMOS. We then formulate the adder design as a dynamic programming problem, optimizing with respect to time. As a result, we have found the fastest 32-bit CMOS adder in our design family.

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BibTeX citation:

@techreport{Wei:CSD-86-252,
    Author= {Wei, Belle W. Y. and Thompson, Clark D. and Chen, Yih-Farn},
    Title= {Time-Optimal Design of a CMOS Adder},
    Year= {1986},
    Month= {Aug},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/6094.html},
    Number= {UCB/CSD-86-252},
    Abstract= {In this paper, we present a systematic method of implementing a VLSI parallel adder. First, we define a family of adders, based on a modular design. Our design uses three types of component cells, which we implement in static CMOS.  We then formulate the adder design as a dynamic programming problem, optimizing with respect to time. As a result, we have found the fastest 32-bit CMOS adder in our design family.},
}

EndNote citation:

%0 Report
%A Wei, Belle W. Y. 
%A Thompson, Clark D. 
%A Chen, Yih-Farn 
%T Time-Optimal Design of a CMOS Adder
%I EECS Department, University of California, Berkeley
%D 1986
%@ UCB/CSD-86-252
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/6094.html
%F Wei:CSD-86-252