Richard L. Rudell
EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M86/65
June 1986
http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/ERL-86-65.pdf
Multiple-valued logic minimization is an important technique for reducing the area required by a Programmable Logic Array (PLA). This report describes both heuristic and exact algorithms for solving the multiple-valued logic minimization problem. These algorithms have been implemented in a C program called Espresso-MV. I
BibTeX citation:
@techreport{Rudell:M86/65, Author = {Rudell, Richard L.}, Title = {Multiple-Valued Logic Minimization for PLA Synthesis}, Institution = {EECS Department, University of California, Berkeley}, Year = {1986}, Month = {Jun}, URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/734.html}, Number = {UCB/ERL M86/65}, Abstract = {Multiple-valued logic minimization is an important technique for reducing the area required by a Programmable Logic Array (PLA). This report describes both heuristic and exact algorithms for solving the multiple-valued logic minimization problem. These algorithms have been implemented in a C program called Espresso-MV. I} }
EndNote citation:
%0 Report %A Rudell, Richard L. %T Multiple-Valued Logic Minimization for PLA Synthesis %I EECS Department, University of California, Berkeley %D 1986 %@ UCB/ERL M86/65 %U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/734.html %F Rudell:M86/65