Logic Verification and Test Generation for VLSI Circuits
Ruey-Sing Wei
EECS Department, University of California, Berkeley
1986
Advisors: Alberto L. Sangiovanni-Vincentelli
BibTeX citation:
@phdthesis{Wei:7691,
Author= {Wei, Ruey-Sing},
Title= {Logic Verification and Test Generation for VLSI Circuits},
School= {EECS Department, University of California, Berkeley},
Year= {1986},
}
EndNote citation:
%0 Thesis %A Wei, Ruey-Sing %T Logic Verification and Test Generation for VLSI Circuits %I EECS Department, University of California, Berkeley %D 1986 %F Wei:7691