Walter Hollingsworth and Howard Sachs and Alan Jay Smith

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-87-329

, 1987

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/CSD-87-329.pdf

The Fairchild CLIPPER microprocessor is a new high performance three chip module consisting of a microprocessor chip and two cache and memory management CAMMU chips, mounted on a small PC board. CLIPPER implements a new instruction set architecture which has been designed for high performance, convenient programmability, broad functionality and sufficient architectural "openness" to permit future evolution and a variety of implementations. <p> In this paper, we (a) describe the instruction set architecture of CLIPPER, (b) describe the chip design architecture and the interesting features of the implementation, and (c) consider in some detail the reasons for various design decisions and tradeoffs. Performance estimates are provided. Possible future directions for both performance and instruction set architecture are outlined. Some comments on the RISC vs. CISC issue are given.

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BibTeX citation:

@techreport{Hollingsworth:CSD-87-329,
    Author= {Hollingsworth, Walter and Sachs, Howard and Smith, Alan Jay},
    Title= {The Fairchild CLIPPER: Instruction Set Architecture and Processor Implementation},
    Year= {1987},
    Month= {Feb},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/5629.html},
    Number= {UCB/CSD-87-329},
    Abstract= {The Fairchild CLIPPER microprocessor is a new high performance three chip module consisting of a microprocessor chip and two cache and memory management CAMMU chips, mounted on a small PC board. CLIPPER implements a new instruction set architecture which has been designed for high performance, convenient programmability, broad functionality and sufficient architectural "openness" to permit future evolution and a variety of implementations.  <p>  In this paper, we (a) describe the instruction set architecture of CLIPPER, (b) describe the chip design architecture and the interesting features of the implementation, and (c) consider in some detail the reasons for various design decisions and tradeoffs. Performance estimates are provided. Possible future directions for both performance and instruction set architecture are outlined. Some comments on the RISC vs. CISC issue are given.},
}

EndNote citation:

%0 Report
%A Hollingsworth, Walter 
%A Sachs, Howard 
%A Smith, Alan Jay 
%T The Fairchild CLIPPER: Instruction Set Architecture and Processor Implementation
%I EECS Department, University of California, Berkeley
%D 1987
%@ UCB/CSD-87-329
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/5629.html
%F Hollingsworth:CSD-87-329