Fred W. Obermeier and Randy H. Katz

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-87-388

, 1987

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/CSD-87-388.pdf

Electrical performance and area improvement are important parts of the overall VLSI design task. Given designer specified constraints on area, delay, and power, EPOXY will size a circuit's transistors and will attempt small circuit changes to help meet the constraints. In addition, the system provides a flexible framework within which to evaluate the effects of different area and electrical models, as well as different optimization algorithms. Since the sum of transistor area is a better measure of dynamic power than cell area, an area model for standard-cell layout is presented. Optimization of a CMOS eight-stage inverter chain illustrates this difference; a typical minimum power implementation is 32.3% larger than the one for minimum area. The combination of a TILOS-style heuristic and augmented Lagrangian optimization algorithm yields quality results rapidly. EPOXY's circuit analysis is from 5 to 56 times faster than Crystal.

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BibTeX citation:

@techreport{Obermeier:CSD-87-388,
    Author= {Obermeier, Fred W. and Katz, Randy H.},
    Title= {EPOXY: An Electrical and Physical Layout Optimizer that Considers Circuit Changes},
    Year= {1987},
    Month= {Nov},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/5851.html},
    Number= {UCB/CSD-87-388},
    Abstract= {Electrical performance and area improvement are important parts of the overall VLSI design task. Given designer specified constraints on area, delay, and power, EPOXY will size a circuit's transistors and will attempt small circuit changes to help meet the constraints. In addition, the system provides a flexible framework within which to evaluate the effects of different area and electrical models, as well as different optimization algorithms. Since the sum of transistor area is a better measure of dynamic power than cell area, an area model for standard-cell layout is presented. Optimization of a CMOS eight-stage inverter chain illustrates this difference; a typical minimum power implementation is 32.3% larger than the one for minimum area. The combination of a TILOS-style heuristic and augmented Lagrangian optimization algorithm yields quality results rapidly. EPOXY's circuit analysis is from 5 to 56 times faster than Crystal.},
}

EndNote citation:

%0 Report
%A Obermeier, Fred W. 
%A Katz, Randy H. 
%T EPOXY: An Electrical and Physical Layout Optimizer that Considers Circuit Changes
%I EECS Department, University of California, Berkeley
%D 1987
%@ UCB/CSD-87-388
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/5851.html
%F Obermeier:CSD-87-388