Glenn D. Adams

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-87-311
August 1986

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/CSD-87-311.pdf

This report describes the internal organization of the SPUR floating point chip. The primary representation of the FPU microarchitecture is its functional level executable hardware description. This description serves as the primary chip design verification tool at both the functional and the layout levels. The text of this paper gives the operation sequence for the chip's instructions and details its datapath and control structures.

BibTeX citation:

@techreport{Adams:CSD-87-311,
    Author = {Adams, Glenn D.},
    Title = {Functional Specification and Simulation of a Floating Point Co-Processor for SPUR},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1986},
    Month = {Aug},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/5985.html},
    Number = {UCB/CSD-87-311},
    Abstract = {This report describes the internal organization of the SPUR floating point chip. The primary representation of the FPU microarchitecture is its functional level executable hardware description. This description serves as the primary chip design verification tool at both the functional and the layout levels. The text of this paper gives the operation sequence for the chip's instructions and details its datapath and control structures.}
}

EndNote citation:

%0 Report
%A Adams, Glenn D.
%T Functional Specification and Simulation of a Floating Point Co-Processor for SPUR
%I EECS Department, University of California, Berkeley
%D 1986
%@ UCB/CSD-87-311
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/5985.html
%F Adams:CSD-87-311