Gaetano Borriello, Andrew Cherenson, Peter B. Danzig and Michael Nelson

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-87-314
October 1986

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/CSD-87-314.pdf

This study compares the performance of executing Prolog code on the Berkeley PLM processor (a special-purpose CISC architecture) and the Berkeley SPUR processor (a general-purpose RISC architecture with tagged data). Fourteen standard benchmark programs were run on both the PLM and SPUR simulators. The two implementations were compared with regard to static and dynamic program size, execution speed, and cache performance. The simulated memory system included a direct-mapped mixed instruction and data cache. We found that, on average, the macro-coded SPUR implementation has a static code size 14 times larger than the PLM, executes 16 times more instructions, yet requires only 2.31 times the number of machine cycles. To have the same miss ratio with a much larger code size the SPUR implementation requires a cache that is 4 to 8 times that of the PLM. We also suggest minor changes to the SPUR instruction set to improve its Prolog execution and outline the design of a special-purpose SPUR coprocessor that would greatly reduce the code size and double SPUR's Prolog performance.

BibTeX citation:

@techreport{Borriello:CSD-87-314,
    Author = {Borriello, Gaetano and Cherenson, Andrew and Danzig, Peter B. and Nelson, Michael},
    Title = {Special- or General-Purpose Hardware for Prolog: A Comparison},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1986},
    Month = {Oct},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/6008.html},
    Number = {UCB/CSD-87-314},
    Abstract = {This study compares the performance of executing Prolog code on the Berkeley PLM processor (a special-purpose CISC architecture) and the Berkeley SPUR processor (a general-purpose RISC architecture with tagged data). Fourteen standard benchmark programs were run on both the PLM and SPUR simulators. The two implementations were compared with regard to static and dynamic program size, execution speed, and cache performance. The simulated memory system included a direct-mapped mixed instruction and data cache. We found that, on average, the macro-coded SPUR implementation has a static code size 14 times larger than the PLM, executes 16 times more instructions, yet requires only 2.31 times the number of machine cycles. To have the same miss ratio with a much larger code size the SPUR implementation requires a cache that is 4 to 8 times that of the PLM. We also suggest minor changes to the SPUR instruction set to improve its Prolog execution and outline the design of a special-purpose SPUR coprocessor that would greatly reduce the code size and double SPUR's Prolog performance.}
}

EndNote citation:

%0 Report
%A Borriello, Gaetano
%A Cherenson, Andrew
%A Danzig, Peter B.
%A Nelson, Michael
%T Special- or General-Purpose Hardware for Prolog: A Comparison
%I EECS Department, University of California, Berkeley
%D 1986
%@ UCB/CSD-87-314
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/6008.html
%F Borriello:CSD-87-314