Patrick C. McGeer, William R. Bush, Gino Cheng and Alvin M. Despain

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-87-363
July 1987

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/CSD-87-363.pdf

The Topolog module generator is the major circuit-design component of the ASP silicon compiler. Topolog is an attempt to determine the utility of Prolog specifically and logic programming generally for the programming of solutions to large-scale VLSI circuit design problems. We have verified that Prolog's clause-based programming style permits easy extensibility of VLSI module generators for new technologies and user-written macroblocks. We have demonstrated that Prolog, even without the well-known assert retract, and write operators is not a pure applicative language. We have devised a method of type definition in Prolog, and have preliminary evidence that our method is superior in efficiency to the general term unification method commonly found in the literature.

BibTeX citation:

@techreport{McGeer:CSD-87-363,
    Author = {McGeer, Patrick C. and Bush, William R. and Cheng, Gino and Despain, Alvin M.},
    Title = {Prolog for VLSI Layout: Experience in the Design and Implementation of Topolog, A Prolog-Based Module Generation and Layout System},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1987},
    Month = {Jul},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/6228.html},
    Number = {UCB/CSD-87-363},
    Abstract = {The Topolog module generator is the major circuit-design component of the ASP silicon compiler. Topolog is an attempt to determine the utility of Prolog specifically and logic programming generally for the programming of solutions to large-scale VLSI circuit design problems. We have verified that Prolog's clause-based programming style permits easy extensibility of VLSI module generators for new technologies and user-written macroblocks. We have demonstrated that Prolog, even without the well-known assert retract, and write operators is not a pure applicative language. We have devised a method of type definition in Prolog, and have preliminary evidence that our method is superior in efficiency to the general term unification method commonly found in the literature.}
}

EndNote citation:

%0 Report
%A McGeer, Patrick C.
%A Bush, William R.
%A Cheng, Gino
%A Despain, Alvin M.
%T Prolog for VLSI Layout: Experience in the Design and Implementation of Topolog, A Prolog-Based Module Generation and Layout System
%I EECS Department, University of California, Berkeley
%D 1987
%@ UCB/CSD-87-363
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1987/6228.html
%F McGeer:CSD-87-363