Gaetano Borriello

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-88-430
May 1988

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/CSD-88-430.pdf

In this dissertation, I present a new methodology for the abstract specification of digital circuit interfaces. An interface is the collection of signal wires that cross a circuit boundary and the constraints on the events on those wires. The specification methodology is based on a formalization of the timing diagrams commonly used by digital circuit designers. This mostly graphical method is not only familiar to its intended users but is also concise in its description. An interactive editor, called Waves, has been implemented to support this methodology and used to describe a wide range of circuit interfaces ranging from static memories, to microprocessors, to system busses.

Interface specification has a wide range of uses during the design and evaluation of a circuit. Waves diagrams and the constraints they capture form the basis for an entire new set of CAD tools that reason about interface design, synthesis, evaluation, and testing. One of these applications, the automatic synthesis of interface transducers, is highlighted in this dissertation.

An interface transducer is the collection of logic circuitry that connects two compatible circuit interfaces. In general, it includes both synchronous and asynchronous components and must satisfy the timing constraints of both interfaces. Interface transducers are required whenever a custom chip is integrated into a computer system or in general, whenever two circuit blocks need to be connected. Their automatic design can greatly reduce the time required to assemble systems or integrate new components into existing systems.

Janus uses a novel approach, based on a small set of templates, to synthesize mixed asynchronous and synchronous control logic. The synthesis algorithm, called Suture, first constructs a skeletal circuit and then locally modifies the design to meet interface timing constraints and eliminate internal race conditions. Optimizations of the resulting sequential logic yield transducers that are comparable in both size and performance to those generated by experienced designers. Three practical examples are used to demonstrate this result.

Advisor: Randy H. Katz

BibTeX citation:

@phdthesis{Borriello:CSD-88-430,
    Author = {Borriello, Gaetano},
    Title = {A New Interface Specification Methodology and its Application to Transducer Synthesis},
    School = {EECS Department, University of California, Berkeley},
    Year = {1988},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/5639.html},
    Number = {UCB/CSD-88-430},
    Abstract = {In this dissertation, I present a new methodology for the abstract specification of digital circuit interfaces. An interface is the collection of signal wires that cross a circuit boundary and the constraints on the events on those wires. The specification methodology is based on a formalization of the timing diagrams commonly used by digital circuit designers. This mostly graphical method is not only familiar to its intended users but is also concise in its description. An interactive editor, called Waves, has been implemented to support this methodology and used to describe a wide range of circuit interfaces ranging from static memories, to microprocessors, to system busses. <p>Interface specification has a wide range of uses during the design and evaluation of a circuit. Waves diagrams and the constraints they capture form the basis for an entire new set of CAD tools that reason about interface design, synthesis, evaluation, and testing. One of these applications, the automatic synthesis of interface transducers, is highlighted in this dissertation. <p>An interface transducer is the collection of logic circuitry that connects two compatible circuit interfaces. In general, it includes both synchronous and asynchronous components and must satisfy the timing constraints of both interfaces. Interface transducers are required whenever a custom chip is integrated into a computer system or in general, whenever two circuit blocks need to be connected. Their automatic design can greatly reduce the time required to assemble systems or integrate new components into existing systems. <p>Janus uses a novel approach, based on a small set of templates, to synthesize mixed asynchronous and synchronous control logic. The synthesis algorithm, called Suture, first constructs a skeletal circuit and then locally modifies the design to meet interface timing constraints and eliminate internal race conditions. Optimizations of the resulting sequential logic yield transducers that are comparable in both size and performance to those generated by experienced designers. Three practical examples are used to demonstrate this result.}
}

EndNote citation:

%0 Thesis
%A Borriello, Gaetano
%T A New Interface Specification Methodology and its Application to Transducer Synthesis
%I EECS Department, University of California, Berkeley
%D 1988
%@ UCB/CSD-88-430
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/5639.html
%F Borriello:CSD-88-430