David A. Wood and Susan J. Eggers and Garth A. Gibson

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-88-394

, 1988

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/CSD-88-394.pdf

This document describes the memory system architecture of the SPUR workstation. SPUR is a bus-based multiprocessor, with caches to reduce each processor's bandwidth requirement. A hardware cache coherency protocol maintains a consistent image of memory across all the caches. A novel address translation scheme eliminates the need for translation buffers. <p>This document is intended as a reference for system and diagnostic programmers. It describes the cache coherency protocol, address translation algorithm, and exception handling mechanisms in detail.

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BibTeX citation:

@techreport{Wood:CSD-88-394,
    Author= {Wood, David A. and Eggers, Susan J. and Gibson, Garth A.},
    Title= {SPUR Memory System Architecture},
    Year= {1988},
    Month= {Jan},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/5856.html},
    Number= {UCB/CSD-88-394},
    Abstract= {This document describes the memory system architecture of the SPUR workstation. SPUR is a bus-based multiprocessor, with caches to reduce each processor's bandwidth requirement. A hardware cache coherency protocol maintains a consistent image of memory across all the caches. A novel address translation scheme eliminates the need for translation buffers. <p>This document is intended as a reference for system and diagnostic programmers. It describes the cache coherency protocol, address translation algorithm, and exception handling mechanisms in detail.},
}

EndNote citation:

%0 Report
%A Wood, David A. 
%A Eggers, Susan J. 
%A Gibson, Garth A. 
%T SPUR Memory System Architecture
%I EECS Department, University of California, Berkeley
%D 1988
%@ UCB/CSD-88-394
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/5856.html
%F Wood:CSD-88-394