Wen-mei William Hwu

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-88-398
January 1988

This dissertation demonstrates that substantial speedup over conventional single-chip microarchitectures can be achieved by a single-chip microarchitecture exploiting deep pipelining, out-of-order execution, multiple operations per instruction, and multiple function units. We have measured the speedup one can potentially achieve with a microarchitecture exploiting local parallelism. We have developed a checkpoint repair mechanism to demonstrate that a microarchitecture exploiting local parallelism need not suffer from inconsistent states when exceptions occur. HPSm, a single-chip microarchitecture, has been designed as the first prototype of our execution model exploiting local parallelism. Experiments have been conducted to demonstrate the effectiveness of HPSm as compared to a popular single-chip microarchitecture, the Berkeley RISC/SPUR. Evaluations have been done with both control intensive and floating point intensive benchmarks. For both types of benchmarks, the HPSm microarchitecture achieves significant speedup over the Berkeley RISC/SPUR implemented with the same fabrication technology.

BibTeX citation:

@techreport{Hwu:CSD-88-398,
    Author = {Hwu, Wen-mei William},
    Title = {Exploiting Concurrency to Achieve High Performance in a Single-chip Microarchitecture},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1988},
    Month = {Jan},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/5869.html},
    Number = {UCB/CSD-88-398},
    Abstract = {This dissertation demonstrates that substantial speedup over conventional single-chip microarchitectures can be achieved by a single-chip microarchitecture exploiting deep pipelining, out-of-order execution, multiple operations per instruction, and multiple function units. We have measured the speedup one can potentially achieve with a microarchitecture exploiting local parallelism. We have developed a checkpoint repair mechanism to demonstrate that a microarchitecture exploiting local parallelism need not suffer from inconsistent states when exceptions occur. HPSm, a single-chip microarchitecture, has been designed as the first prototype of our execution model exploiting local parallelism.  Experiments have been conducted to demonstrate the effectiveness of HPSm as compared to a popular single-chip microarchitecture, the Berkeley RISC/SPUR. Evaluations have been done with both control intensive and floating point intensive benchmarks. For both types of benchmarks, the HPSm microarchitecture achieves significant speedup over the Berkeley RISC/SPUR implemented with the same fabrication technology.}
}

EndNote citation:

%0 Report
%A Hwu, Wen-mei William
%T Exploiting Concurrency to Achieve High Performance in a Single-chip Microarchitecture
%I EECS Department, University of California, Berkeley
%D 1988
%@ UCB/CSD-88-398
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/5869.html
%F Hwu:CSD-88-398