Garth A Gibson

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-88-480

, 1988

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/CSD-88-480.pdf

This document specifies the design of a shared system bus for a synchronous multiprocessor based on shared memory. The bus is called the SpurBus and it is part of the SPUR, Symbolic Processing Using RISCs, project [Hill86, Ouster88, Wood87]. SPUR is a multiprocessor workstation. Each processor is a RISC, Reduced Instruction Set Computer, with a tagged architecture for supporting the LISP programming environment {Taylor86} and an instruction buffer to reduce instruction traffic across chip borders [Hill87]. Each node in the multiprocessor contains a processor, a large cache (128 KB), a floating point coprocessor and a cache controller. The controller and across the bus. The goal of SPUR is to provide a low cost, fast microprocessor with additional processors available for research efforts into shared memory multiprocessing. The number of processors is small (6 to 12) so that a low cost interconnect, the system bus, will be able to supply the required memory bandwidth. Conceptually, a system bus is a simple flexible, reliable, convenient point of serialization for synchronization and monitoring and, most important, its design can be borrowed from existing microcomputer system buses.

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BibTeX citation:

@techreport{Gibson:CSD-88-480,
    Author= {Gibson, Garth A},
    Title= {SpurBus Specification: SPUR, Symbolic Processing Using RISC, Project},
    Year= {1988},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/6052.html},
    Number= {UCB/CSD-88-480},
    Abstract= {This document specifies the design of a shared system bus for a synchronous multiprocessor based on shared memory. The bus is called the SpurBus and it is part of the SPUR, Symbolic Processing Using RISCs, project [Hill86, Ouster88, Wood87]. SPUR is a multiprocessor workstation. Each processor is a RISC, Reduced Instruction Set Computer, with a tagged architecture for supporting the LISP programming environment {Taylor86} and an instruction buffer to reduce instruction traffic across chip borders [Hill87]. Each node in the multiprocessor contains a processor, a large cache (128 KB), a floating point coprocessor and a cache controller. The controller and across the bus. The goal of SPUR is to provide a low cost, fast microprocessor with additional processors available for research efforts into shared memory multiprocessing. The number of processors is small (6 to 12) so that a low cost interconnect, the system bus, will be able to supply the required memory bandwidth. Conceptually, a system bus is a simple flexible, reliable, convenient point of serialization for synchronization and monitoring and, most important, its design can be borrowed from existing microcomputer system buses.},
}

EndNote citation:

%0 Report
%A Gibson, Garth A 
%T SpurBus Specification: SPUR, Symbolic Processing Using RISC, Project
%I EECS Department, University of California, Berkeley
%D 1988
%@ UCB/CSD-88-480
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/6052.html
%F Gibson:CSD-88-480