Randy H. Katz and John L. Hennessy

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-89-529

, 1989

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/CSD-89-529.pdf

Single chip processor performance has improved dramatically since the inception of the four-bit microprocessor in 1971. This is due in part to technological advances, (i.e., faster devices and greater device density), but also because of the adoption of architectural approaches well suited to the opportunities and limitations of VLSI. The most appropriate are those that effectively reduce off-chip memory accesses and admit of a regular pipelined implementation. The overriding goal of pipelining is to achieve "single cycle execution," i.e., instructions appear to execute in a single processor cycle. Today's RISC processors are close to realizing this goal, and the next generation will reduce the cycles per instruction even further. In this paper, we will review the design issues and the proposed architectures for high performance VLSI processors.

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BibTeX citation:

@techreport{Katz:CSD-89-529,
    Author= {Katz, Randy H. and Hennessy, John L.},
    Title= {High Performance Microprocessor Architectures},
    Year= {1989},
    Month= {Aug},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/5898.html},
    Number= {UCB/CSD-89-529},
    Abstract= {Single chip processor performance has improved dramatically since the inception of the four-bit microprocessor in 1971. This is due in part to technological advances, (i.e., faster devices and greater device density), but also because of the adoption of architectural approaches well suited to the opportunities and limitations of VLSI. The most appropriate are those that effectively reduce off-chip memory accesses and admit of a regular pipelined implementation. The overriding goal of pipelining is to achieve "single cycle execution," i.e., instructions appear to execute in a single processor cycle. Today's RISC processors are close to realizing this goal, and the next generation will reduce the cycles per instruction even further. In this paper, we will review the design issues and the proposed architectures for high performance VLSI processors.},
}

EndNote citation:

%0 Report
%A Katz, Randy H. 
%A Hennessy, John L. 
%T High Performance Microprocessor Architectures
%I EECS Department, University of California, Berkeley
%D 1989
%@ UCB/CSD-89-529
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/5898.html
%F Katz:CSD-89-529