Georges E. Smine and Vason P. Srini

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-89-531

, 1989

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/CSD-89-531.pdf

Semi-custom design of high-performance VLSI processors has been demonstrated by the Berkeley VLSI-PLM chip using Mentor Graphics IDEA station, Cell station tools and NCR tools. To support semi-custom design using Berkeley VLSI tools such as LagerIV, we have developed a set of cells. These cells are designed with the goal of designing a high-performance VLSI Parallel Prolog Processor. They can be used in other designs such as DSP chips. Some of these cells complement those in LagerIV's DPP cell library. Others provide an area efficient replacement for the DPP cells.

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BibTeX citation:

@techreport{Smine:CSD-89-531,
    Author= {Smine, Georges E. and Srini, Vason P.},
    Title= {Area Efficient Cells for LagerIV's DPP Library},
    Year= {1989},
    Month= {Aug},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/5912.html},
    Number= {UCB/CSD-89-531},
    Abstract= {Semi-custom design of high-performance VLSI processors has been demonstrated by the Berkeley VLSI-PLM chip using Mentor Graphics IDEA station, Cell station tools and NCR tools. To support semi-custom design using Berkeley VLSI tools such as LagerIV, we have developed a set of cells. These cells are designed with the goal of designing a high-performance VLSI Parallel Prolog Processor. They can be used in other designs such as DSP chips. Some of these cells complement those in LagerIV's DPP cell library. Others provide an area efficient replacement for the DPP cells.},
}

EndNote citation:

%0 Report
%A Smine, Georges E. 
%A Srini, Vason P. 
%T Area Efficient Cells for LagerIV's DPP Library
%I EECS Department, University of California, Berkeley
%D 1989
%@ UCB/CSD-89-531
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/5912.html
%F Smine:CSD-89-531