Lau T. Nguyen, Linda G. Bushnell and Vason P. Srini

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-89-496
March 1989

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/CSD-89-496.pdf

We present the details of the design, simulation, construction, and testing of the VLSI-PLM Board. The VLSI-PLM Board is a wire-wrapped processor board for the VLSI-PLM Chip, a high performance CMOS processor for executing computer programs written in the Prolog language. All work was performed at the University of California at Berkeley. The design and simulations were performed using Mentor Graphics Computer Aided Design (CAD) tools on Apollo workstations. By using these tools, we were able to draw the gate-level design schematics on the computer and simulate the functionality and timing of the design. After the gate-level design passed all simulation tests, a wire-wrapped board was constructed with assistance from the Electronics Research Lab of the Electrical Engineering and Computer Science (EECS) Department. This wire-wrapped board was tested using a custom-made tester panel. The wire-wrapped board tests verified the computer simulations of the gate-level design. The total wire-wrapped part occupies 18 cm by 22 cm in a board 40 cm by 36 cm, with a total of 95 Integrated Circuit (IC) chips including the VLSI-PLM Chip.

BibTeX citation:

@techreport{Nguyen:CSD-89-496,
    Author = {Nguyen, Lau T. and Bushnell, Linda G. and Srini, Vason P.},
    Title = {The VLSI-PLM Board: Design, Construction, and Testing},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1989},
    Month = {Mar},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/6152.html},
    Number = {UCB/CSD-89-496},
    Abstract = {We present the details of the design, simulation, construction, and testing of the VLSI-PLM Board. The VLSI-PLM Board is a wire-wrapped processor board for the VLSI-PLM Chip, a high performance CMOS processor for executing computer programs written in the Prolog language. All work was performed at the University of California at Berkeley. The design and simulations were performed using Mentor Graphics Computer Aided Design (CAD) tools on Apollo workstations. By using these tools, we were able to draw the gate-level design schematics on the computer and simulate the functionality and timing of the design. After the gate-level design passed all simulation tests, a wire-wrapped board was constructed with assistance from the Electronics Research Lab of the Electrical Engineering and Computer Science (EECS) Department. This wire-wrapped board was tested using a custom-made tester panel. The wire-wrapped board tests verified the computer simulations of the gate-level design. The total wire-wrapped part occupies 18 cm by 22 cm in a board 40 cm by 36 cm, with a total of 95 Integrated Circuit (IC) chips including the VLSI-PLM Chip.}
}

EndNote citation:

%0 Report
%A Nguyen, Lau T.
%A Bushnell, Linda G.
%A Srini, Vason P.
%T The VLSI-PLM Board: Design, Construction, and Testing
%I EECS Department, University of California, Berkeley
%D 1989
%@ UCB/CSD-89-496
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/6152.html
%F Nguyen:CSD-89-496