A VLSI Chip Set for a Mutiprocessor Workstation
Daebum Lee and Deog-Kyoon Jeong and David A. Wood and David A. Patterson and Mark D. Hill and Shing I. Kong and George S. Taylor and David A. Hodges and Susan J. Eggers and Garth A. Gibson and Randy H. Katz
EECS Department, University of California, Berkeley
Technical Report No. UCB/CSD-89-500
, 1989
http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/CSD-89-500.pdf
This two-part paper describes two key components used in building a 40-70 MIPS multiprocessor workstation. In the first part, VLSI implementation of the central processing unit (CPU) chip, based on reduced instruction set computer (RISC) architecture and with support for LISP is described. The 1.3cm^2 CPU chip uses a direct-mapped 512-byte on-chip instruction cache, and 138 40-bit registers organized in 8 overlapping windows to achieve 10 MIPS per processor peak performance with a 10 MHz, four-phase clock. <p>The second part of the paper describes the memory management unit and cache controller (MMU/CC) chip. System level design issues such as multiprocessor cache coherency and synchronization among chip sets are also considered in the second part. Both chips are implemented in a 1.6 um double-layer-metal CMOS technology, and are being used in a multiprocessor workstation (SPUR) successfully executing its own operating system called Sprite as well as many applications including LISP programs. <p><strong>Part I title:</strong> A RISC Microprocessor with Coprocessor Interface and Support for Symbolic Testing <br /><strong>Part II title:</strong> A Memory Management Unit and Cache Controller
BibTeX citation:
@techreport{Lee:CSD-89-500,
Author= {Lee, Daebum and Jeong, Deog-Kyoon and Wood, David A. and Patterson, David A. and Hill, Mark D. and Kong, Shing I. and Taylor, George S. and Hodges, David A. and Eggers, Susan J. and Gibson, Garth A. and Katz, Randy H.},
Title= {A VLSI Chip Set for a Mutiprocessor Workstation},
Year= {1989},
Month= {Apr},
Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/6153.html},
Number= {UCB/CSD-89-500},
Abstract= {This two-part paper describes two key components used in building a 40-70 MIPS multiprocessor workstation. In the first part, VLSI implementation of the central processing unit (CPU) chip, based on reduced instruction set computer (RISC) architecture and with support for LISP is described. The 1.3cm^2 CPU chip uses a direct-mapped 512-byte on-chip instruction cache, and 138 40-bit registers organized in 8 overlapping windows to achieve 10 MIPS per processor peak performance with a 10 MHz, four-phase clock. <p>The second part of the paper describes the memory management unit and cache controller (MMU/CC) chip. System level design issues such as multiprocessor cache coherency and synchronization among chip sets are also considered in the second part. Both chips are implemented in a 1.6 um double-layer-metal CMOS technology, and are being used in a multiprocessor workstation (SPUR) successfully executing its own operating system called Sprite as well as many applications including LISP programs. <p><strong>Part I title:</strong> A RISC Microprocessor with Coprocessor Interface and Support for Symbolic Testing <br /><strong>Part II title:</strong> A Memory Management Unit and Cache Controller},
}
EndNote citation:
%0 Report %A Lee, Daebum %A Jeong, Deog-Kyoon %A Wood, David A. %A Patterson, David A. %A Hill, Mark D. %A Kong, Shing I. %A Taylor, George S. %A Hodges, David A. %A Eggers, Susan J. %A Gibson, Garth A. %A Katz, Randy H. %T A VLSI Chip Set for a Mutiprocessor Workstation %I EECS Department, University of California, Berkeley %D 1989 %@ UCB/CSD-89-500 %U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/6153.html %F Lee:CSD-89-500