Min-Chie Jeng

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M90/90
October 1990

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1990/ERL-90-90.pdf

A photoresist ashing technique has been developed which, when used in conjunction with conventional optical lithography, permits controlled definition of the gate of deep-submicrometer MOSFETs. This technique can also be extended to other lithographic processes, such as e-beam and x-ray. Comprehensive studies based on the performance and hot-electron reliability have shown that the basic physics associated with deep-submicrometer devices is similar to that of their longer-channel counterparts. Therefore, existing device design guidelines and models can still be used with minor modifications. A set of design curves has been generated based on experimental results with various mechanisms under consideration. With these design curves, the trade-offs between device dimensions and power supply for a particular technology can be observed. The relative importance of each mechanism can also be identified.

A semi-empirical MOSFET drain current model accurate down to quarter-micron channels, suitable for digital as well as analog applications has been developed. Both the drain current and the output resistance are accurately modeled. The first derivative of the drain current equation is continuous from the subthreshold region to the strong-inversion region and from the linear region to the saturation region for all biases. This model has been implemented in SPICE3. A parameter extraction system dedicated to the model was also developed.

Advisor: Ping K. Ko

BibTeX citation:

@phdthesis{Jeng:M90/90,
    Author = {Jeng, Min-Chie},
    Title = {Design and Modeling of Deep-Submicrometer MOSFETs},
    School = {EECS Department, University of California, Berkeley},
    Year = {1990},
    Month = {Oct},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1990/1601.html},
    Number = {UCB/ERL M90/90},
    Abstract = {A photoresist ashing technique has been developed which, when
used in conjunction with conventional optical lithography, permits
controlled definition of the gate of deep-submicrometer MOSFETs.
This technique can also be extended to other lithographic processes,
such as e-beam and x-ray. Comprehensive studies based on the
performance and hot-electron reliability have shown that the basic
physics associated with deep-submicrometer devices is similar to
that of their longer-channel counterparts.  Therefore, existing
device design guidelines and models can still be used with minor
modifications. A set of design curves has been generated based on
experimental results with various mechanisms under consideration.
With these design curves, the trade-offs between device dimensions
and power supply for a particular technology can be observed.
The relative importance of each mechanism can also be identified.

A semi-empirical MOSFET drain current model accurate down to
quarter-micron channels, suitable for digital as well as analog
applications has been developed.  Both the drain current and the
output resistance are accurately modeled.  The first derivative
of the drain current equation is continuous from the subthreshold
region to the strong-inversion region and from the linear region
to the saturation region for all biases.  This model has been
implemented in SPICE3. A parameter extraction system dedicated to
the model was also developed.}
}

EndNote citation:

%0 Thesis
%A Jeng, Min-Chie
%T Design and Modeling of Deep-Submicrometer MOSFETs
%I EECS Department, University of California, Berkeley
%D 1990
%@ UCB/ERL M90/90
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1990/1601.html
%F Jeng:M90/90