Ping-San Tzeng

EECS Department, University of California, Berkeley

Technical Report No. UCB/CSD-92-689

, 1992

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1992/CSD-92-689.pdf

This dissertation investigates ways to integrate various VLSI layout algorithms via carefully designed integrated data structures. Such an integrated approach can achieve better overall results by iterating non-sequentially among the various algorithms in a demand-driven manner. The shared data structure which is modified incrementally by all the different algorithms serves as an efficient communication medium between them. This approach has resulted in several new prototype tools, including a new placement program that combines wire-length optimization with a new 2-D compaction algorithm, a new area-routing approach that employs hierarchical rip-up and reroute techniques in an integrated global and detailed routing environment, and also a system that integrates the area router with a placement adjustment algorithm. This integrated system can iterate automatically between area routing and placement adjustment phases to generate optimized results for macro-cell problems with over-the-cell routing.

Advisors: Carlo H. Séquin

---

BibTeX citation:

@phdthesis{Tzeng:CSD-92-689,
    Author= {Tzeng, Ping-San},
    Title= {Integrated Placement and Routing for VLSI Layout Synthesis and Optimization},
    School= {EECS Department, University of California, Berkeley},
    Year= {1992},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1992/6245.html},
    Number= {UCB/CSD-92-689},
    Abstract= {This dissertation investigates ways to integrate various VLSI layout algorithms via carefully designed integrated data structures. Such an integrated approach can achieve better overall results by iterating non-sequentially among the various algorithms in a demand-driven manner. The shared data structure which is modified incrementally by all the different algorithms serves as an efficient communication medium between them. This approach has resulted in several new prototype tools, including a new placement program that combines wire-length optimization with a new 2-D compaction algorithm, a new area-routing approach that employs hierarchical rip-up and reroute techniques in an integrated global and detailed routing environment, and also a system that integrates the area router with a placement adjustment algorithm. This integrated system can iterate automatically between area routing and placement adjustment phases to generate optimized results for macro-cell problems with over-the-cell routing.},
}

EndNote citation:

%0 Thesis
%A Tzeng, Ping-San 
%T Integrated Placement and Routing for VLSI Layout Synthesis and Optimization
%I EECS Department, University of California, Berkeley
%D 1992
%@ UCB/CSD-92-689
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1992/6245.html
%F Tzeng:CSD-92-689