Timothy H.-T. Hu

EECS Department, University of California, Berkeley

Technical Report No. UCB/ERL M93/62

, 1993

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/ERL-93-62.pdf

Reduction in cost terminal electronics is essential in order for fiber optic technology to penetrate LAN and telephony subscriber loop applications extensively. Currently, high-data-rate fiber transceivers electronics are implemented principally with the multichip approach, with bipolar and gallium arsenide technology. The objective of this research is to develop a new parallel architecture to use the lower cost and higher integration of scaled CMOS technology to address the cost problem in fiber transceivers. The problem is first attacked by integrating the parallel-to-serial conversion, automatic gain control (AGC), decision, and clock recovery functions in CMOS at rates about 500Mb/s. The inherently slower speed of CMOS compared to bipolar and GaAs is compensated through the use of a high degree of parallel signal processing in the signal path. To verify the main idea about the new parallel architecture proposed in this thesis, an experimental prototype with 8 parallel channels was designed and fabricated in a 1.2um CMOS technology. A bit rate of 480 MB/s is achieved with a minimum peak-to-peak input voltage of 18mV. The area of the chip is 160 milX160 mil(4mm X 4 mm) and it consumes 900mW of power. This thesis arrives at three main conclusions. First a minimum device f(T) to data rate ratio of 4:1 can be achieved with the parallel architecture enabling CMOS technology to be used for Gb/s digital optical fiber receivers. Second, clock recovery can be done, through a decision directed scheme with two times over-sampling, by inserting one or more timing channels in between the parallel data channels. Finally, the area and power consumption of the parallel architecture are comparable to implementations in bipolar and GaAs.

Advisors: Paul R. Gray

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BibTeX citation:

@phdthesis{Hu:M93/62,
    Author= {Hu, Timothy H.-T.},
    Title= {A Parallel Architecture for High-Data-Rate Digital Receivers in Scaled CMOS Technology},
    School= {EECS Department, University of California, Berkeley},
    Year= {1993},
    Month= {Jul},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2418.html},
    Number= {UCB/ERL M93/62},
    Abstract= {Reduction in cost terminal electronics is essential in order for fiber optic technology to penetrate LAN and telephony subscriber loop applications extensively.  Currently, high-data-rate fiber transceivers electronics are implemented principally with the multichip approach, with bipolar and gallium arsenide technology.  The objective of this research is to develop a new parallel architecture to use the lower cost and higher integration of scaled CMOS technology to address the cost problem in fiber transceivers.  The problem is first attacked by integrating the parallel-to-serial conversion, automatic gain control (AGC), decision, and clock recovery functions in CMOS at rates about 500Mb/s.  The inherently slower speed of CMOS compared to bipolar and GaAs is compensated through the use of a high degree of parallel signal processing in the signal path.  To verify the main idea about the new parallel architecture proposed in this thesis, an experimental prototype with 8 parallel channels was designed and fabricated in a 1.2um CMOS technology.  A bit rate of 480 MB/s is achieved with a minimum peak-to-peak input voltage of 18mV. The area of the chip is 160 milX160 mil(4mm X 4 mm) and it consumes 900mW of power.  This thesis arrives at three main conclusions.  First a minimum device f(T) to data rate ratio of 4:1 can be achieved with the parallel architecture enabling CMOS technology to be used for Gb/s digital optical fiber receivers. Second, clock recovery can be done, through a decision directed scheme with two times over-sampling, by inserting one or more timing channels in between the parallel data channels.  Finally, the area and power consumption of the parallel architecture are comparable to implementations in bipolar and GaAs.},
}

EndNote citation:

%0 Thesis
%A Hu, Timothy H.-T. 
%T A Parallel Architecture for High-Data-Rate Digital Receivers in Scaled CMOS Technology
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/62
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2418.html
%F Hu:M93/62