Y. Sakina

EECS Department, University of California, Berkeley

Technical Report No. UCB/ERL M93/63

, 1993

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/ERL-93-63.pdf

The single-bit second-order A/D architecture is very attractive for medium-speed and high-resolution conversion (e.g. 14 bits, 80ksamples/second for 1.75 um CMOS technology) and many signal processing systems with this architecture have become available recently. However, its performance is not sufficient to accomplish faster and high-resolution conversion. In this report, we propose a new architecture to improve the performance. We use a multi-bit modulator and see the feasibility of realizing high performance. The performance of multi-bit converters is generally degraded by internal DAC nonlinearity due to element mismatch. In the light of this we introduced the dynamic barrel shifting for the allocation of unit elements of the DAC so that we can minimize this degradation. This dynamic allocation pushed the noise due to the nonlinearity out of the baseband, which results in the improvement of the signal to noise ratio (SNR). A system-level simulator for the four-bit modulator is developed to analyze the behavior of the modulator. The results from the simulation show that the new four-bit modulator can reduce the degradation due to the element mismatch, which results in the better SNR than randomization. However, the SNR falls short of the ideal case of perfectly matched elements in the DAC. Analog-circuit requirements for a CMOS circuit implementation are also presented.

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BibTeX citation:

@techreport{Sakina:M93/63,
    Author= {Sakina, Y.},
    Title= {Multi-Bit SIGMA DELTA Analog-to-Digital Converters with Nonlinearity Correction Using Dynamic Barrel Shifting},
    Year= {1993},
    Month= {Jul},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2419.html},
    Number= {UCB/ERL M93/63},
    Abstract= {The single-bit second-order A/D architecture is very attractive for medium-speed and high-resolution conversion (e.g. 14 bits, 80ksamples/second for 1.75 um CMOS technology) and many signal processing systems with this architecture have become available recently.  However, its performance is not sufficient to accomplish faster and high-resolution conversion.  In this report, we propose a new architecture to improve the performance.  We use a multi-bit modulator and see the feasibility of realizing high performance.  The performance of multi-bit converters is generally degraded by internal DAC nonlinearity due to element mismatch.  In the light of this we introduced the dynamic barrel shifting for the allocation of unit elements of the DAC so that we can minimize this degradation.  This dynamic allocation pushed the noise due to the nonlinearity out of the baseband, which results in the improvement of the signal to noise ratio (SNR).  A system-level simulator for the four-bit modulator is developed to analyze the behavior of the modulator.  The results from the simulation show that the new four-bit modulator can reduce the degradation due to the element mismatch, which results in the better SNR than randomization.  However, the SNR falls short of the ideal case of perfectly matched elements in the DAC.  Analog-circuit requirements for a CMOS circuit implementation are also presented.},
}

EndNote citation:

%0 Report
%A Sakina, Y. 
%T Multi-Bit SIGMA DELTA Analog-to-Digital Converters with Nonlinearity Correction Using Dynamic Barrel Shifting
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/63
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2419.html
%F Sakina:M93/63