Low-Power High-Speed DSP Architecture for Magnetic Disk PRML Read Channel

S-H.C. Wong

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M93/72
October 1993

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/ERL-93-72.pdf

As a result of the rapid development of disk technology, several orders of magnitude improvement in storage density has been made on magnetic disk systems in the last few decades. Currently state-of-the-art disk systems can store up to 350 millions bits per square inch. By the end of this decade, it is predicted that the maximum storage density will be increased to 10 billions bits per square inch. To take advantage of this tremendous increase in disk storage density, there must be a comparable improvement in processing power of the associated electronics. In this report, a parallel DSP architecture, which provides the key functions required in the magnetic disk read channel employing Class IV Partial Response Signalling, will be presented. To greatly enhance the throughput of the DSP, the proposed architecture creates four time-interleaved channels which allow parallel processing of signal. In certain applications such as portable computers, it is essential to cut down the power dissipation of the disk drive electronics. This report will discuss the advantage of using the parallel architecture from a low-power design point of view, despite that it consumes more silicon area. A prototype with an adaptive equalizer and a Class IV Partial Response Viterbi decoder was fabricated in a standard MOSIS 1.2um CMOS process. The total silicon area is 57,000 mil squared (36.6 mm squared). Experimental results show that the chip can achieve a throughput of 50MBits/sec with a power consumption of 70.5mW only.

BibTeX citation:

@techreport{Wong:M93/72,
    Author = {Wong, S-H.C.},
    Title = {Low-Power High-Speed DSP Architecture for Magnetic Disk PRML Read Channel},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1993},
    Month = {Oct},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2434.html},
    Number = {UCB/ERL M93/72},
    Abstract = {As a result of the rapid development of disk technology, several orders of magnitude improvement in storage density has been made on magnetic disk systems in the last few decades. Currently state-of-the-art disk systems can store up to 350 millions bits per square inch. By the end of this decade, it is predicted that the maximum storage density will be increased to 10 billions bits per square inch. To take advantage of this tremendous increase in disk storage density, there must be a comparable improvement in processing power of the associated electronics. In this report, a parallel DSP architecture, which provides the key functions required in the magnetic disk read channel employing Class IV Partial Response Signalling, will be presented. To greatly enhance the throughput of the DSP, the proposed architecture creates four time-interleaved channels which allow parallel processing of signal. In certain applications such as portable computers, it is essential to cut down the power dissipation of the disk drive electronics. This report will discuss the advantage of using the parallel architecture from a low-power design point of view, despite that it consumes more silicon area. A prototype with an adaptive equalizer and a Class IV Partial Response Viterbi decoder was fabricated in a standard MOSIS 1.2um CMOS process.  The total silicon area is 57,000 mil squared (36.6 mm squared). Experimental results show that the chip can achieve a throughput of 50MBits/sec with a power consumption of 70.5mW only.}
}

EndNote citation:

%0 Report
%A Wong, S-H.C.
%T Low-Power High-Speed DSP Architecture for Magnetic Disk PRML Read Channel
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/72
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2434.html
%F Wong:M93/72