Brian D. N. Lee

EECS Department, University of California, Berkeley

Technical Report No. UCB/ERL M93/81

, 1993

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/ERL-93-81.pdf

The integrated circuit layout problem is the specification of fabrication patterns that implement a given circuit description subject to manufacturing and performance constraints. The high complexity of integrated circuits has made it necessary to decompose the layout problem into a set of subproblems, and the typical layout process usually solves a sequence of subproblems corresponding to the steps of floor planning, placement, channel definition, global routing, detailed routing, and compaction. Each subproblem depends on the solutions of the previous subproblems and iteration over the sequence of problems may be required to find a feasible layout solution. Unfortunately, iterative improvement of layout solutions is very difficult because a side effect of the partitioning is that feedback between subproblems is hard and not well understood. A merged hierarchial approach to layout presented that provides a means of investigating the relationship between placement and routing to improve current layout methods. A common data model is used to integrate layout phases and to simplify and enhance information flow within the layout process. The data model induces a structure to the layout process for experimenting with feedback and information management. A layout system based on a 2x2 grid-graph abstraction that combines placement and global routing has been implemented based on this paradigm. Examples from sea-of-gates designs are used for benchmark comparisons.

Advisors: A. Richard Newton

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BibTeX citation:

@phdthesis{Lee:M93/81,
    Author= {Lee, Brian D. N.},
    Title= {Combined Hierarchical Approaches to Integrated Circuit Layout Based on a Common Data Model},
    School= {EECS Department, University of California, Berkeley},
    Year= {1993},
    Month= {Nov},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2453.html},
    Number= {UCB/ERL M93/81},
    Abstract= {The integrated circuit layout problem is the specification of fabrication patterns that implement a given circuit description subject to manufacturing and performance constraints. The high complexity of integrated circuits has made it necessary to decompose the layout problem into a set of subproblems, and the typical layout process usually solves a sequence of subproblems corresponding to the steps of floor planning, placement, channel definition, global routing, detailed routing, and compaction. Each subproblem depends on the solutions of the previous subproblems and iteration over the sequence of problems may be required to find a feasible layout solution. Unfortunately, iterative improvement of layout solutions is very difficult because a side effect of the partitioning is that feedback between subproblems is hard and not well understood. A merged hierarchial approach to layout presented that provides a means of investigating the relationship between placement and routing to improve current layout methods. A common data model is used to integrate layout phases and to simplify and enhance information flow within the layout process. The data model induces a structure to the layout process for experimenting with feedback and information management. A layout system based on a 2x2 grid-graph abstraction that combines placement and global routing has been implemented based on this paradigm. Examples from sea-of-gates designs are used for benchmark comparisons.},
}

EndNote citation:

%0 Thesis
%A Lee, Brian D. N. 
%T Combined Hierarchical Approaches to Integrated Circuit Layout Based on a Common Data Model
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/81
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2453.html
%F Lee:M93/81