A Physical Poly-Silicon Thin Film Transistor (TFT) Model for Circuit Simulation

C. Li

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M93/82
November 1993

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/ERL-93-82.pdf

This report presents a poly-silicon thin film transistors model for circuit simulations. The drain current model includes the effects of hot carrier, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is linked to the drain current and its derivatives. This model has been implemented in SPICE. Simulation and experimental results are compared.

BibTeX citation:

@techreport{Li:M93/82,
    Author = {Li, C.},
    Title = {A Physical Poly-Silicon Thin Film Transistor (TFT) Model for Circuit Simulation},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1993},
    Month = {Nov},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2454.html},
    Number = {UCB/ERL M93/82},
    Abstract = {This report presents a poly-silicon thin film transistors model for circuit simulations.  The drain current model includes the effects of hot carrier, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL).  The capacitance model is linked to the drain current and its derivatives.  This model has been implemented in SPICE. Simulation and experimental results are compared.}
}

EndNote citation:

%0 Report
%A Li, C.
%T A Physical Poly-Silicon Thin Film Transistor (TFT) Model for Circuit Simulation
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/82
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2454.html
%F Li:M93/82